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[HeXus]Legendary CPU architect Jim Keller leaves AMD - Page 22

post #211 of 284
Quote:
Originally Posted by Redwoodz View Post

Do we really know if HBM2 tech could not overcome the latency penalty?

We know that the speed of electric signals through several centimeters of copper is an insurmountable barrier to the sort of latency required for a high-speed CPU cache, especially at the lower levels.

No memory standard in existence, nor any conceivable memory standard that could exist according to the laws of nature, as we know them, would make it viable to move anything but the very last levels of cache (main memory, and in some systems, a buffer or memory controller) off package.

The round trip time for an electromagnetic wave, at the speed of light, to something right next to the socket would already be more than 50% of the total latency of current L1 caches, and a significant fraction of the total latency of L2.
Edited by Blameless - 9/21/15 at 11:57am
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post #212 of 284
Quote:
Originally Posted by infranoia View Post

Jim gives his engineering love freely, to the highest bidder. OK, fair enough-- this news alone isn't good or bad.

But for AMD, no news is good news, and this is news. It would be better if they could go into radio silence until the next process is out.
How does this relate to Microsoft possibly purchasing AMD? They have endless amounts of money. Anyone see this as a possible connection?
post #213 of 284
im no expert but i heard at least part of the problems with bulldozer was they had to cut stuff it needed to be faster, because the die would have been to big, if they would have had access to a better fab to make it the way they wanted and die shrunk it, Bulldozer might have come out better
post #214 of 284
Quote:
Originally Posted by Thready View Post

I just hear people sometimes saying AMD can't be doing bad because they're making the new console chips, but doesn't the real money come from newly designed products? I don't know that much about tech business so I was just wondering.

The real money comes when R&D and initial production costs have been recouped. Selling legacy products is like icing on the cake that's already been baked.
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post #215 of 284
Quote:
Originally Posted by Blameless View Post

We know that the speed of electric signals through several centimeters of copper is an insurmountable barrier to the sort of latency required for a high-speed CPU cache, especially at the lower levels.

No memory standard in existence, nor any conceivable memory standard that could exist according to the laws of nature, as we know them, would make it viable to move anything but the very last levels of cache (main memory, and in some systems, a buffer or memory controller) off package.

The round trip time for an electromagnetic wave, at the speed of light, to something right next to the socket would already be more than 50% of the total latency of current L1 caches, and a significant fraction of the total latency of L2.

Fiber optics?
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post #216 of 284
Hopefullness
Jim left
Cold dawn
Silvermont starts shine

/Unknown Zen-master/
post #217 of 284
Quote:
Originally Posted by Redwoodz View Post

Do we really know if HBM2 tech could not overcome the latency penalty?
L1 and L2 can for sure not be replaced any time soon if ever. L3 in Bulldozer's implementation might as well not be there at all since it's so broken but in Zen it is allegedly fixed and thus L3 can't be replaced also. So what remains is the optional L4 just like Intel does.
Quote:
Originally Posted by Blameless View Post

The round trip time for an electromagnetic wave, at the speed of light, to something right next to the socket would already be more than 50% of the total latency of current L1 caches, and a significant fraction of the total latency of L2.
First of all just say light to keep things simple. Second let's say the distance traveled is 2 cm so the total shortest path would be 0,04 m.
0,04 / 297.000.000 m/s = 1,3 * 10^-10 seconds in other words 0,13 * 10^-9 aka ns.
That's a fraction of 50% of the total latency we see today. For reference Intel's L1 cache on Haswell is about 1 ns. But yeah if you mean with right next to the socket 10 cm away then sure.

Anyways we agree it's not going to happen luckily for the world the future needs bandwidth usually more than just low latency but it's dependent on what you're doing. CPU tasks prefer low latency while gpu task prefer higher bandwidth at the cost of higher latency.
Quote:
Originally Posted by Redwoodz View Post

Fiber optics?
You will still have to go back to electrical signals at one point
Edited by maarten12100 - 9/21/15 at 4:43pm
post #218 of 284
Quote:
Originally Posted by Alastair View Post

It isn't really bad news at all. He has seen to the completion of ZEN. So what's he supposed to do now? Sit on his butt while AMD refines the ZEN core for the next 4 years?

thats such a bad business strategy.

if a company wants to progress continuously, they shouldn't just stop and sit doing nothing after finishing one project, they have to immediately start on a new one.

look at Intel, they're doing 3~4 architectures at the same time on different groups, e.g. even when Haswell was in development they were already doing Skylake.
Edited by epic1337 - 9/21/15 at 5:22pm
post #219 of 284
Quote:
Originally Posted by Redwoodz View Post

Fiber optics?

I was already assuming speed of light.
Quote:
Originally Posted by maarten12100 View Post

That's a fraction of 50% of the total latency we see today. For reference Intel's L1 cache on Haswell is about 1 ns. But yeah if you mean with right next to the socket 10 cm away then sure.

I was assuming ~5cm of traces for the shortest practical length to attach an HBM stack that would still be off package. So yeah, a 10cm round trip sounds about right.
Edited by Blameless - 9/21/15 at 5:00pm
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post #220 of 284
I did read all the 11 pages so far and my opinion differs.

First, from the very beginning it was clear to me, Zen was all about making Atom-like cluster CPU, pretty much as Phi family, the second fastest supercomputer is running AMD CPUs for a reason, yet as one superb article emerged&stated the new AMD CPU has to form the base for the exascale computing, petascale aged already wink.gif
Fellow members talk/speculate Zen having 4 up to 8 cores, no, no and no, I believe having less than 16 (even as an initial variant) goes against its philosophy - many power-efficient cores.

My take on this fishy situation.

- Jim Keller was fired having firm/unmovable view about how Zen should be developed. Perhaps the shareholders and their captain asked him to compromise here-and-there and deliver the product early regardless of current obstacles. He strikes me as having quite different persona than servants chasing careers/money first products/legacy next.

- As far as I see, he wanted to make the analogue (more lite, though) to Intel's "Knights Landing" in form of Zen replacing Silvermont.

http://www.datacenterdynamics.com/it-networks/intels-knights-landing-can-run-240-threads/93641.fullarticle

The situation resembles this top-to-down pressure - our guy having strangled on the ropes had to quit, I guess.

4899721-1348610645852024-Mike-Rest.jpg

The AMD's comment sounds very unfriendly, to me. Every cheap detective novels reader would see the possibility of showing the door to the employee refusing to bend. My plan was to buy Zen, now I think not. If the true reason for departure surfaces then surely I should like to hear it. Good guys should get all support possible - not the servile moneymakers. thumb.gif
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