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post #101 of 443
Quote:
Originally Posted by sugarhell View Post

More CEs is impossible because the maximum is 4 with GCN.

Interesting. What's the limiting factor keeping them from putting more CEs and linking them on the same part?

I was under the impression that these architectures, indeed most modern processor architectures, were highly modular, and could be made to scale to nearly any arbitrary unit count, interconnects and transistor budgets permitting.
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post #102 of 443
Quote:
Originally Posted by Blameless View Post

Interesting. What's the limiting factor keeping them from putting more CEs and linking them on the same part?

I was under the impression that these architectures, indeed most modern processor architectures, were highly modular, and could be made to scale to nearly any arbitrary unit count, interconnects and transistor budgets permitting.

I dont know exactly why. I think it has to do how every single part of gcn communicate with each other, To increase the number of compute engine probably will have to increase and everything else like data share components and etc etc etc. That means a major architecture change.

FRom anand:
Quote:
At the time of the Hawaii launch AMD told us that the GCN 1.1 architecture had a maximum scalability of 4 shader engines

http://www.anandtech.com/show/9390/the-amd-radeon-r9-fury-x-review/4
Edited by sugarhell - 9/24/15 at 11:28am
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post #103 of 443
Quote:
Originally Posted by sugarhell View Post

I dont know exactly why. I think it has to do how every single part of gcn communicate with each other, To increase the number of compute engine probably will have to increase and everything else like data share components and etc etc etc. That means a major architecture change.

FRom anand:
http://www.anandtech.com/show/9390/the-amd-radeon-r9-fury-x-review/4

Thanks for the info.

A limit of four SE's, if still present, would seem to be becoming a significant problem for the scalability of GCN.
Edited by Blameless - 9/24/15 at 11:37am
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post #104 of 443
Quote:
Originally Posted by sugarhell View Post

I dont know exactly why. I think it has to do how every single part of gcn communicate with each other, To increase the number of compute engine probably will have to increase and everything else like data share components and etc etc etc. That means a major architecture change.

http://www.anandtech.com/show/9390/the-amd-radeon-r9-fury-x-review/4
Quote:
Originally Posted by Blameless View Post

That just implies a different balance (fewer) of shaders per CE, and more CEs, would have been more optimal in (pixel) fill rate limited scenarios.
So is 96 ROPs.
Quote:
These 64 CUs in turn are laid out in a manner consistent with past GCN designs, with AMD retaining their overall Shader Engine organization. Sub-dividing the GPU into four parts, each shader engine possesses 1 geometry unit, 1 rasterizer unit, 4 render backends (for a total of 16 ROPs), and finally, one-quarter of the CUs, or 16 CUs per shader engine. The CUs in turn continue to be organized in groups of 4, with each group sharing a 16KB L1 scalar cache and 32KB L1 instruction cache. Meanwhile since Fiji’s CU count is once again a multiple of 16, this also does away with Hawaii’s oddball group of 3 CUs at the tail-end of each shader engine.

also from anandtech
Quote:
Getting away from the CUs for a second, the R9 Fury X features less dramatic changes at its front-end and back-end relative to Hawaii. Like Hawaii, R9 Fury X features 4 geometry engines on the front-end and 64 ROPs on the back-end, so from a theoretical standpoint Fiji does not have any additional resources to work with on those portions of the rendering pipeline. That said, what the raw specifications do not cover are the architectural optimizations we have covered in past pages, which should see Fiji’s ROPs and geometry engines both perform better per unit and per clock than Hawaii’s. Meanwhile the other significant influence here is the extensive memory bandwidth enabled by using High Bandwidth Memory, which combined with a larger 2MB L2 cache should leave the ROPs far better fed on R9 Fury X than it did on AMD’s Hawaii cards

http://www.anandtech.com/show/9390/the-amd-radeon-r9-fury-x-review/10
post #105 of 443
Quote:
Originally Posted by Bryanud View Post

They are using a pre-overclocked asus. You could argue for or against it since many consumer 980tis are like this... and many people buying these enthusiast top of the line cards are the type to manually overclock anyway.

Anyway, in an odd way I find it satisfying that these results mirror the trends we saw from the ashes benchmarks. The 290s/390s do really well, the FuryX catches up to the 980ti, and the rest of Nvidia's lineup are a little lacking by comparison. I like the consistency smile.gif
And they are using refference fury and 390/X ....... i remebred they are no refference 390x and fury biggrin.gif
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post #106 of 443
Quote:
Originally Posted by Blameless View Post

Thanks for the info.

A limit of four SE's, if still present, would seem to be becoming a significant problem for the scalability of GCN.

Probably we will see this problem solved with the new gpus and new GCN.
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post #107 of 443
Quote:
Originally Posted by sugarhell View Post

Probably we will see this problem solved with the new gpus and new GCN.
I hope Post GCN arch will solve this problem, im realy optimistic about the upcoming arctic islands gpus smile.gif
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post #108 of 443
Both AMD and Nvidia have probably designed upcoming GPUs with DX12 in mind. Anything else would be stupid
post #109 of 443
Quote:
Originally Posted by iLeakStuff View Post

Holy hell thats a huge advantage for the 980Ti eh-smiley.gif

Techreport is using the ASUS Strix 980Ti which is about 20% OC over the Stock

Stock 980Ti would probably be ahead anyways but not nearly as much
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post #110 of 443
Until you oc maxwell(what they excel at) then it's game over.
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