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[Various] AMD's Zen To Have 10 Pipelines Per Core - Details Leaked In Patch (Updated)

post #1 of 758
Thread Starter 
Quote:
A lot of the new functionality has been filed for patenting. For example there was a mention of checkpointing, which is good for quick reversion of mispredicted branches and other reasons for restarting the pipelines. Some patents suggest, that Zen might use some slightly modified Excavator branch prediction.

And the new patch also suggests nicely low int/fp mul, fp add, int/fp div and fp square root latencies. Some of these lower latencies (div/sqrt) were introduced with Excavator, as an Aida64 instruction latency dump provided by Anandtech forum user monstercameron revealed. Due to an Aida problem with measured and reported clock frequencies (although it was fixed at 1.4GHz), you have to multiply the measured times by 1.4 to get the real number of cycles. Ok, back to Zen.

Here are some quotes of the patch file:

  1. Decoders unit has 4 decoders and all of them can decode fast path
  2. and vector type instructions.
  3. Integer unit 4 ALU pipes.
  4. 2 AGU pipes.
  5. Floating point unit 4 FP pipes.
  6. 32, /* size of l1 cache. */
  7. 512, /* size of l2 cache. */

Excerpt:
  1. 4 wide decoders
  2. 4 integer ALUs
  3. 2 AGUs (for 2R 1W L1 cache according to a LinkedIn profile)
  4. 4 FP pipelines
  5. That makes z ten pipelines with a general four wide design.


Interestingly, as there are two 128b FP mul and two 128b FP add units (with only 3 cycles latency for these ops), the FMA instructions will be executed by combining one FP MUL and one FP ADD unit, resulting in 2 issues and 5 cycles latency (as that of the Bulldozer family). This saves some register file ports and increases throughput and reduces latencies of the more common FP ops. It even remembers me of the bridged FMA unit.

These latencies also clearly suggest, that this is no high clock frequency design. But at 14nm (or 16nm from TSMC as some rumours suggest) clocks of 3.5 to 4 GHz should be reachable without stretching the thermal limits too much.

Here is a schematic, which should come close to what Zen might really look like:


Quote:
Bulldozer module:

Core1: 2 ALU + 2 AGU
Core2: 2 ALU + 2 AGU
FPU: 2 128bit FMAC + 2 MMX
Instruction Decode: 4 Wide
L1 Cache: 64 KB Instruction per module + 16 KB data per core
L2 Cache: 2 MB

Zen core:

Core1: 4 ALU + 2 AGU
FPU: 2 128bit FMAC (2 128bit add + 2 128bit mul)
Instruction Decode: 4 Wide
L1 Cache: 32 KB data + ?
L2 Cache: 512 KB

Haswell core:

Core1: 4 ALU + 4 AGU
FPU: 2 256bit FMAC (256bit add + 256bit mul)
Instruction Decode: 4 Wide
L1 Cache: 32 KB Instruction + 32 KB Data
L2 Cache: 256 KB

Source 1: http://dresdenboy.blogspot.com/2015/10/amds-zen-core-family-17h-to-have-ten.html

For reference, Sandy Bridge has 6, Haswell has 8 (Broadwell, and Skylake included) and Piledriver has 4+4 that are shared with another core. Translation, one Zen core can execute multiple non related commands simultaneously; meaning integer operations, floating point operations, and moving data from and to memory. Based on the article, it has 4 instruction decoders/hyperthreads per core, all of which support decoding fast path and vector instructions. Each core has 4 ALUs, meaning you can run 4 integer operations on an ALU simultaneously, and the same for the FPUs as well as floating point operations.

Seems there is more to add to this Blog post via WCCF Tech:
Quote:

AMD has just uploaded a patch to the patchwork project detailing many aspects of its hotly anticipated Zen CPU microarchitecture.

The patch was uploaded by venkataramanan.kumar@amd.com and is titled ” [x86_64] znver1 enablement” re-affirming that there will be indeed multiple generations of AMD’s brand new CPU core and this particular patch only covers the first iteration of the core that’s coming out next year.

The Patch Allows Us To Get A Glimpse Into The Inner-Workings Of AMD’s Next Generation High Performance x86 Zen CPU Core Today, with the information that has been revealed through the patch, we can get a better idea of how Zen looks like from a high-level design standpoint.
Quote:
+;; Integer unit 4 ALU pipes.

+(define_cpu_unit "znver1-ieu0" "znver1_ieu")

+(define_cpu_unit "znver1-ieu1" "znver1_ieu")

+(define_cpu_unit "znver1-ieu2" "znver1_ieu")

+(define_cpu_unit "znver1-ieu3" "znver1_ieu")

+(define_reservation "znver1-ieu" "znver1-ieu0|znver1-ieu1|znver1-ieu2|znver1-ieu3")

+

+;; 2 AGU pipes.

+(define_cpu_unit "znver1-agu0" "znver1_agu")

+(define_cpu_unit "znver1-agu1" "znver1_agu")

+(define_reservation "znver1-agu-reserve" "znver1-agu0|znver1-agu1")
Floating point unit 4 FP pipes.

+(define_cpu_unit "znver1-fp0" "znver1_fp")

+(define_cpu_unit "znver1-fp1" "znver1_fp")

+(define_cpu_unit "znver1-fp2" "znver1_fp")

+(define_cpu_unit "znver1-fp3" "znver1_fp")

+

+(define_reservation "znver1-fpu" "znver1-fp0|znver1-fp1|znver1-fp2|znver1-fp3")

This gives us a beautifully high-level insight into what a Zen core looks like. Each core has four ALU pipes , two AGU pipes and four FP pipes. ALU is short for Arithmetic Logic Unit, AGU is short for Address Generation Unit and FP is short for Floating Point. The four ALU pipes in this context represent the core’s integer pipeline and the four FP pipes represent the floating point pipeline inside the core’s Floating Point Unit. The AGU’s work in tandem with the integer front-end to facilitate communication between the ALUs and a II-read, I-write L1 cache according to an AMD engineer’s linkedin profile that Mr. Waldhauer has spotted.

If we create a diagram of the core’s high-level design based on the Integer and Floating Point pipes mentioned in the patch then we get something that looks like this :



For a better perspective we put Zen side to side with AMD’s steamroller, as the company has not published a block diagram for Excavator unfortunately. However according to what AMD revealed at this past Hot Chips, Excavator should have a very similar high-level layout to Steamroller. A just quick note to refresh everyone’s memory, Steamroller is the CPU core that AMD has introduced with its 7000 series Kaveri and Godavari APUs.



The first thing that is easily discernible is that there is only one integer cluster in a Zen core rather than two like there is in a Steamroller module. These two integer clusters in Steamroller are what forms the two separate CPU cores / threads in each module. Zen takes on a more traditional AMD CPU layout resembling that of Phenom and Athlon K series cores. With a single Integer cluster and one equally large floating point unit.

Zen forgoes the CMT design of the bulldozer family we Zen should have a single fetch and a single decode unit in the front end, as opposed to the double decoders that were introduced with Steamroller. Comparing both floating point units, with four FP pipes Zen’s floating point is effectively twice as wide as that of Steamroller.



Interestingly, the two 128-bit FMAC units in the Bulldozer family can process one 128-bit SIMD instruction per cycle each ot fuse together to process a single 256-bit AVX instruction per cycle.



If this capability to fuse and process larger instructions is carried over to Zen it would enable the two 256-bit FMAC units – 4 128-bit pipes – to fuse and process 512bit AVX instructions. Which would make the core compatible with Intel’s AVX512 instruction set extension. Which is currently only supported by Intel’s Knight’s Landing Xeon Phi microarchitecture.

The wider floating point unit also means that Zen will be able to process less complex instructions at double the rate of Steamroller A massive boost in floating point performance, an area where AMD had historically excelled in with Phenom II and prior CPUs.

There was also one particularly important improvement with Zen that Mr. Waldhauer has managed to spot in a number of patents filed by AMD CPU engineers working on Zen.

A lot of the new functionality has been filed for patenting. For example there was a mention of checkpointing, which is good for quick reversion of mispredicted branches and other reasons for restarting the pipelines. Some patents suggest, that Zen might use some slightly modified Excavator branch prediction.

The branch misprediction penalty on the Bulldozer family of cores was a particularly significant one due to the deep piped nature of the microarchitecture. Intel’s Sandy Bridge, which was introduced to the market at the same time as Bulldozer, had an equally deep pipeline. However with Sandy Bridge Intel introduced a micro-op cache which significantly contributed to reducing the performance penalty of mispredicting a branch. Zen should be AMD’s first CPU core which would see the introduction of a technology that might not be similar to the solution on Sandy Bridge but is still focused solely on reducing branch misprediction penalties.

In summary, compared to Bulldozer family cores, Zen has double the floating point pipes as well as a better way of handling mispredicted branches, coupled with a more streamlined front-end as well as faster and more efficient cache sub-systems. All of these combined have undoubtedly contributed to the massive 40% IPC improvement that AMD has announced back in May.

Source 2: http://wccftech.com/amd-zen-cpu-core-microarchitecture-detailed/2/

Source 3: https://patchwork.ozlabs.org/patch/524324/

Seems HeXus wants to get in on this too:
Quote:
AMD's first generation Zen processors will have; four instruction decoders, four Integer units (ALUs), two address units (AGUs) and four floating-point units (FP) at 128 bit wide. Compared to Bulldozer and Steamroller, Zen will have double the execution units and quadruple floating point units. SMT, similar to Intel Hyperthreading, will be enabled by Zen. The cache sizes are speculation, just to complete the diagram. Further speculation is that the clock speeds that Zen will run at will be between 3.5 to 4.0GHz – even though it will be manufactured at 14 or 16nm.

Edit Chart 2:



Source 4: http://hexus.net/tech/news/cpu/86954-zen-processor-block-diagram-devised-amd-software-patch/
Edited by BiG StroOnZ - 10/7/15 at 1:31am
post #2 of 758
Looks like AMD's first true four-wide core (Intel's x86 CPUs have been able to retire four instructions per cycle since Core 2) and 8 or 10 execution ports, depending on how you look at things (Haswell has seven).
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post #3 of 758
Cool stuff. Is your use of the term "Hyperthreads" accurate though? My understanding was that hyperthreads basically context switch between two simulated processes on a single physical core, whereas this system seems to actually be able to execute multiple instructions simultaneously.
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post #4 of 758
Why didn't they design it to exceed Haswell's specifications?

Wouldn't they want to match Haswell at least?

ZEN:
Quote:
FPU: 2 128bit FMAC (2 128bit add + 2 128bit mul)

Haswell:
Quote:
FPU: 2 256bit FMAC (256bit add + 256bit mul)

And why not use 384bit or something so it's "better".

(I have no idea how any of this works, please don't kill me if this is a stupid thing to ask).
post #5 of 758
So now we are taking someone's blog as rumor as well?
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post #6 of 758
Quote:
Originally Posted by cookieboyeli View Post

Why didn't they design it to exceed Haswell's specifications?

Wouldn't they want to match Haswell at least?

ZEN:
Haswell:
And why not use 384bit or something so it's "better".

(I have no idea how any of this works, please don't kill me if this is a stupid thing to ask).

you'd end up with a huge die, counter productive to margin and yield per wafer.
or in other words, it gets stupid expensive.

what they'd have to do is aim for the smallest die-size they can design it to, without sacrificing average performance.
in this case, they'd have to make their design more efficient and takes less transistors to perform better.
Edited by epic1337 - 10/4/15 at 7:39am
post #7 of 758
Quote:
Originally Posted by Clocknut View Post

So now we are taking someone's blog as rumor as well?
Technically anything someone says that isn't confirmed is a rumor. I could say that you like to eat golden retriever puppies. Is it true? No (most likely). Is it a credible source in retrospect? No. But that's what makes it a rumor.

It is entirely possible what is shown here is 100% true and on point. Not likely, but possible.
post #8 of 758
Quote:
Originally Posted by cookieboyeli View Post

Why didn't they design it to exceed Haswell's specifications?

Wouldn't they want to match Haswell at least?

ZEN:
Haswell:
And why not use 384bit or something so it's "better".

(I have no idea how any of this works, please don't kill me if this is a stupid thing to ask).

Zen is aimed at servers where scaling isn't as big of an issue as it is with personal-use and hence perf/power means they can scale up more. Given that they're producing Zen on GF's 14nm process they probably can't make something that's both large and efficient. So they're making something kinda big and will most likely be trying to maximize power efficiency.
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post #9 of 758
Quote:
Originally Posted by cookieboyeli View Post

Wouldn't they want to match Haswell at least?

It does, perhaps even exceeds them, if the AVX/AVX2 capabilities are on their own ports.
Quote:
Originally Posted by cookieboyeli View Post

And why not use 384bit or something so it's "better".

Because there are 128-bit, 256-bit, and 512-bit SIMD instruction sets that need to be supported.

384-bit would never be used by any native instruction, and would thus be a less efficient option.
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post #10 of 758
If the price is right AMD could have a hit especialy with an 8 cores 16 threads zen cpu to compete with the i7, and in the end we'll see price drops hopefully thumb.gif
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80go Intel x25 ssd series + 500 go Samsung  cooler master V6 gt Win 7 64bit ultimate edition cooler master silent pro 850w 
Case
HAF 912 advanced 
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Number 3
(16 items)
 
Dust Catcher
(9 items)
 
CPUMotherboardGraphicsRAM
i7 6700k 4.5 ghz MSI Gaming M7  1080ti aorus xtreme 2x8 go Gskill 3200mhz C15 
Hard DriveHard DriveHard DriveHard Drive
crucial ssd 128 Go 2x Samsung 840 evo 250 Go Hitachi HDD 2To Toshiba HDD 2To 
Optical DriveCoolingOSMonitor
Old DVD-RW KRAKEN X61 Windows 10 x64 Swift 2k 165hz 
KeyboardPowerCaseMouse
g910 CM V1000 CM Trooper modded g502 proteus 
CPUMotherboardGraphicsRAM
Phenom ii x6 1075t Asus Sabertooth 990fx CF 2x Asus 6950 directcu ii  2x4Gb Gskill 1333 
Hard DriveCoolingOSPower
80go Intel x25 ssd series + 500 go Samsung  cooler master V6 gt Win 7 64bit ultimate edition cooler master silent pro 850w 
Case
HAF 912 advanced 
  hide details  
Reply
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Overclock.net › Forums › Industry News › Rumors and Unconfirmed Articles › [Various] AMD's Zen To Have 10 Pipelines Per Core - Details Leaked In Patch (Updated)