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[Various] AMD's Zen To Have 10 Pipelines Per Core - Details Leaked In Patch (Updated) - Page 2

post #11 of 758
Very interesting stuff. Where are those "patch notes" coming from ?If its only using 2x128, that wouldn't be too good :/
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post #12 of 758
Quote:
Originally Posted by cookieboyeli View Post

Why didn't they design it to exceed Haswell's specifications?

Wouldn't they want to match Haswell at least?

ZEN:
Haswell:
And why not use 384bit or something so it's "better".

(I have no idea how any of this works, please don't kill me if this is a stupid thing to ask).

I have no idea either lol (but who actually does on OCN?) maybe a higher amount is not needed because the components around it are faster
post #13 of 758
Quote:
Originally Posted by ku4eto View Post

Very interesting stuff. Where are those "patch notes" coming from ?If its only using 2x128, that wouldn't be too good :/

The core design is better than Bulldozer's design philosophy, so i personally would say that not all hope is lost because of 2 x 128.
    
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post #14 of 758
Despite all that, this upcoming AMD CPUs line-up still wont be able to beat Intel in terms of raw performance, will just provide a better price per performance ration until a certain point.
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post #15 of 758
Quote:
Originally Posted by ku4eto View Post

Very interesting stuff. Where are those "patch notes" coming from ?If its only using 2x128, that wouldn't be too good :/

2x128 on this design will be just as effective as 2x256 on Intel's design for all non-AVX instructions.

Zen can also do 4x64 instructions as well, and certain operations should be able to do 8x32 (32-bit being the near-universal floating point size).

I wouldn't be surprised to learn that AMD didn't prioritize AVX performance, with their strong desire to lean on GPU compute (for obvious reasons).

I think they're moving towards being able to directly move certain floating point vector math to the GPU without any special coding tools or compilers needed. All-on-CPU. In theory, it wouldn't be that difficult, but it would absolutely introduce latency, so they would need to be able to fetch a significant amount of instructions and just have the GPU work on all of the likely branches all at once, then when the logic units know which results are needed, simply pull in the finished results. The end result would be an apparent near-zero latency for certain floating point operations thumb.gif
post #16 of 758
Quote:
Originally Posted by cookieboyeli View Post

Why didn't they design it to exceed Haswell's specifications?

Wouldn't they want to match Haswell at least?

ZEN:
Haswell:
And why not use 384bit or something so it's "better".

(I have no idea how any of this works, please don't kill me if this is a stupid thing to ask).

"It's not about how big it is, it's about how you use it." Sort of applies here.

While larger, may equal better, it doesn't have to be that way.

I.E. I could design a CPU with 256MB of L1 cache, and it'd be a damn fine chip. Except it would be so impractical even my grandma would lose her patience trying to open Outlook 2003.

P.S. I'm not sure if this is entirely impossible, I was just hyperbolizing.
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post #17 of 758
Quote:
Originally Posted by Cybertox View Post

Despite all that, this upcoming AMD CPUs line-up still wont be able to beat Intel in terms of raw performance, will just provide a better price per performance ration until a certain point.

It's not that hard to make a cpu that would outperform Intel's.

The hard thing is to make a cpu with that performance that is affordable. It remains to be seen where those lines will cross.
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post #18 of 758
Quote:
Originally Posted by Cybertox View Post

Despite all that, this upcoming AMD CPUs line-up still wont be able to beat Intel in terms of raw performance, will just provide a better price per performance ration until a certain point.

Actually this design appears poised to beat intel CPUs in a good chunk of integer based workloads, and perhaps even 128-bit SIMD. Most likely intel will remain stronger in anything wider, like AVX, but If Zen's 128-bit parts can be effectively combined into 256-bit units (Bulldozer family was awful at that), AMD won't be left too far behind this time round.In any case When it comes to games where AVX is not a thing, Zen might achieve parity with haswell/skylake after all. If Zen doesn't have hidden faults or some major overlook, we might see reviews where AMD and intel trade blows in benchmarks depending on application, and I am talking throughout their whole range of products (since FX8 will be 5960X competitor). not like with bulldozer or piledriver where they could only score some wins vs mainstream SB/IB quad i7s. Provided that GloFo offers a node that allow clocks in the 3.5GHz region that is...

Quote:
Originally Posted by Redwoodz View Post

It's not that hard to make a cpu that would outperform Intel's.

The hard thing is to make a cpu with that performance that is affordable. It remains to be seen where those lines will cross.

That might not be that hard after all. Intel likes to sell their mainstream quads that are designed around laptops to the desktop crowd. Which means half their die or more is the iGPU which many people find unnecessary. AMD could offer four hyperthreaded Zen cores made with 14nm FF of Samsung/GloFo without iGPU at half the price of a 4790k ir 6700k and still be as profitable.
Edited by Kuivamaa - 10/4/15 at 3:12am
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post #19 of 758
I'm sorry for being an idiot, but can someone please explain in laymans terms what this actually means? frown.gif
post #20 of 758
The core can execute 10 functions concurrently. This is instruction level parallelism (doing int/fp/store/etc all at the same time) rather than thread level parallelism that can use more cores.

Think of breaking down a complex algebra problem into chunks that can be done at the same time. (A+B)*(C-D) is a good simple example. You would do A+B and C-D at the same time in the same CPU. Then you could do the multiplication in one of the FPU units to free the other general purpose math pipelines to start the next equation. All of this is decided in the instruction decoder (real time) usually if my memory serves right, rather than the compiler doing the work (pre-computed).
Edited by KarathKasun - 10/4/15 at 4:11am
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