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[Various] AMD's Zen To Have 10 Pipelines Per Core - Details Leaked In Patch (Updated) - Page 70

post #691 of 758
Quote:
Originally Posted by delboy67 View Post

Along with the game engine you'd need your own os/ui and 'to the metal' api specific to your exact hardware effectively creating your own console for one game, with all the open standards I suppose it could be doable but not realistic.
There is a specific gaming market that could be successfully targeted with such a game, one that has been badly exploited and burned by a certain large company.
post #692 of 758
Some others findings by dresdenboy :

AMD Zeppelin CPU codename confirmed by patch and perhaps 32 cores per socket for Zen based MPUs, too

http://dresdenboy.blogspot.de/2016/02/amd-zeppelin-cpu-codename-confirmed-by.html
post #693 of 758
Quote:
Originally Posted by Olivon View Post

Some others findings by dresdenboy :

AMD Zeppelin CPU codename confirmed by patch and perhaps 32 cores per socket for Zen based MPUs, too

http://dresdenboy.blogspot.de/2016/02/amd-zeppelin-cpu-codename-confirmed-by.html
If i understood right, it means 4 cores per module?
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post #694 of 758
Quote:
Originally Posted by ku4eto View Post

If i understood right, it means 4 cores per module?
Appears so. 1 cluster of cores ("Core complex") apparently contains 4 cores, all joined together by a common L3 cache.

The question now is: How many core clusters can AMD shove on a single die?
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post #695 of 758
I think this raises another question. How will the 4 cores split the L3 cache, and how will this affect latency and FPU's.
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post #696 of 758
I thought it was obvious since a long time ago each module was 4 cores?
post #697 of 758
Quote:
Originally Posted by STEvil View Post

I thought it was obvious since a long time ago each module was 4 cores?
I am not sure, i think i may have missed that. At least this is now a confirmation, before it could have been only rumor.
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post #698 of 758
Quote:
Originally Posted by ku4eto View Post

I think this raises another question. How will the 4 cores split the L3 cache, and how will this affect latency and FPU's.
Well (someone correct me if I'm wrong) AMD did develop dynamic resource sharing of the L2 cache for their post Piledriver cores, so it would be logical for them to scale that to the common L3 cache, where the core(s) that need it would get a larger slice of L3, while cores that dont need it get a smaller slice, with it shifting around as needed.

Latency could be interesting. My guess on how it would work is that the latency to the local L3 cache is relatively low, while a snoop of the other L3 caches would incur a higher relative latency penalty, as they'd essentially be "L3.5" caches for cores not directly attached to them. As a result, the memory hierarchy would become: L1 (D/I)->L2->Local L3-> Distal L3(.5)->L4 (if any)->Main memory. The FPUs would end up seeing maximum performance only from the local L3 cache, with a performance hit if checking the other L3 caches is done.
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post #699 of 758
I expect that it would be like how the large Intel chips are like with a ring bus (or other interconnect) linking separate core clusters/l3 cache.

Intel right now has 2 cores having thier own L3 which is then shared among all the cores via 2-3 ring buses.Depending on good thier bus is and how they implement it, the performance hit from accessing other L3 cache might not be so bad.

Biggest question I see is if Zen will have half clusters like 2 cores or 6 or 10.
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post #700 of 758
AMD's last chance, better be something good. Else can throw away.
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