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[Various] AMD's Zen To Have 10 Pipelines Per Core - Details Leaked In Patch (Updated) - Page 8

post #71 of 758
Quote:
Originally Posted by spurdomantbh View Post

I believe they can. But Zen isn't really gimped in AVX2. It can do 2xFADD/FMUL ops just like Haswell. However seems like Haswell can do 2xFMA, while Zen can do 1xFMA. But there might be a typo I think.
Code:
+                     "znver1-double,(znver1-fp0+znver1-fp3)|(znver1-fp1+znver1-fp3)")
Doesn't make much sense. It could be a typo so we still can't be 100% sure how the FPU will work. But either way on most workloads it shouldn't lag behind Haswell.

Wow, yeah, that must be a typo. I'd expect even/odd or adjacent ganging, not fp3 always being ganged. But, if that's the case, then maybe they use fp2 for something else?

Or, maybe, I'm just not understanding what the code is meant to represent.
Edited by looncraz - 10/5/15 at 5:59pm
post #72 of 758
It's going to mainly come down to how much AMD can improve their cache system and memory controller. The Apple chips showed this.
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post #73 of 758
Quote:
Originally Posted by geoxile View Post

Zen is aimed at servers where scaling isn't as big of an issue as it is with personal-use and hence perf/power means they can scale up more. Given that they're producing Zen on GF's 14nm process they probably can't make something that's both large and efficient. So they're making something kinda big and will most likely be trying to maximize power efficiency.

Plus with it aiming up to 16 cores with HT... I highly doubt the need for large cores.
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post #74 of 758
Quote:
Originally Posted by Vesku View Post

It's going to mainly come down to how much AMD can improve their cache system and memory controller. The Apple chips showed this.

They seem to have confidence in their cache if the design is relatively close to Haswell's but double the cache size.
Jim supposedly really likes tuning IMCs, and it shows if his work on Cyclone is anything to go by.

I think the clincher will be the node and how high it clocks.
Edited by PiOfPie - 10/5/15 at 7:20pm
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post #75 of 758
Quote:
Originally Posted by PiOfPie View Post

Quote:
Originally Posted by Vesku View Post

It's going to mainly come down to how much AMD can improve their cache system and memory controller. The Apple chips showed this.

They seem to have confidence in their cache if the design is relatively close to Haswell's but double the cache size.
Jim supposedly really likes tuning IMCs, and it shows if his work on Cyclone is anything to go by.

I think the clincher will be the node and how high it clocks.
Absolutely. Because there's no way they're blowing PAST Kaby Lake, but if it clocks well then it's really going to be a winner. biggrin.gif
Is there anything else on that node we can compare with?
Any clues as to it's potential or downfalls?
post #76 of 758
Thread Starter 
Seems HeXus wants to get in on this too with some more charts:
Quote:
AMD's first generation Zen processors will have; four instruction decoders, four Integer units (ALUs), two address units (AGUs) and four floating-point units (FP) at 128 bit wide. Compared to Bulldozer and Steamroller, Zen will have double the execution units and quadruple floating point units. SMT, similar to Intel Hyperthreading, will be enabled by Zen. The cache sizes are speculation, just to complete the diagram. Further speculation is that the clock speeds that Zen will run at will be between 3.5 to 4.0GHz – even though it will be manufactured at 14 or 16nm.

Edit Chart 2:


Source: http://hexus.net/tech/news/cpu/86954-zen-processor-block-diagram-devised-amd-software-patch/
Edited by BiG StroOnZ - 10/6/15 at 10:27pm
post #77 of 758
Quote:
Originally Posted by cookieboyeli View Post

Absolutely. Because there's no way they're blowing PAST Kaby Lake, but if it clocks well then it's really going to be a winner. biggrin.gif
Is there anything else on that node we can compare with?
Any clues as to it's potential or downfalls?

soldered + good clock per voltage = pure win
AMD's processors had always gotten good clock potential, this is something which could also be expected from Zen.
i just hope AMD doesn't put the base clock at 4Ghz with boost of +500Mhz, that high of a baseclock ruins the fun in overclocking.
Edited by epic1337 - 10/5/15 at 9:36pm
post #78 of 758
Quote:
Originally Posted by epic1337 View Post

soldered + good clock per voltage = pure win
AMD's processors had always gotten good clock potential, this is something which could also be expected from Zen.
i just hope AMD doesn't put the base clock at 4Ghz with boost of +500Mhz, that high of a baseclock ruins the fun in overclocking.
if they put for ex. 3.5GHz, the price gonna be 3.5GHz pricing. I am gonna compare that with the equivalent stock intel cpu performance.

Overclock-ability has always been the last part of the product valuation, right after heat + power consumption.
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post #79 of 758
Relax guys! it is all fine! They had a decade of copying INTEL designs tongue.gif! The same way INTEL copied them in the past smile.gif. The CPU industry has gone full circle smile.gif. Zen will be good and we will ride all our noble steeds into the sunshine!
 
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post #80 of 758
Quote:
Originally Posted by BiG StroOnZ View Post

Seems HeXus wants to get in on this too with some more charts:
Source: http://hexus.net/tech/news/cpu/86954-zen-processor-block-diagram-devised-amd-software-patch/

Hadn't they added two more execution ports with Haswell ? One for ALU and another one for AGU.
or am I missing something ?
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