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[Various] AMD's Zen To Have 10 Pipelines Per Core - Details Leaked In Patch (Updated) - Page 71

post #701 of 758
Quote:
Originally Posted by ku4eto View Post

I think this raises another question. How will the 4 cores split the L3 cache, and how will this affect latency and FPU's.

Just as usual? The L3 cache has always been shared across all the cores. You meant the L2 cache, which was shared between the two ALU clusters in a single module. The only difference then is a single cluster gets the full l2 cache for herself.
post #702 of 758
Quote:
Originally Posted by 2010rig View Post

What is their answer for Skylake?

Being 80% as fast at half the cost is...you'll admit... a fairly good answer.
post #703 of 758
Come on red team, give me something decent and I'm back with y'all. Definitely won't be the first to buy it again this time though like Bulldozer. I'll wait about 2 weeks to get some real numbers then I'll buy in again.
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post #704 of 758
AMD is pretty quiet about ZEN core info... they are only saying 40%+ IPC over excavator.
post #705 of 758
Quote:
Originally Posted by Faithh View Post

Just as usual? The L3 cache has always been shared across all the cores. You meant the L2 cache, which was shared between the two ALU clusters in a single module. The only difference then is a single cluster gets the full l2 cache for herself.

We know from the Linux patch that Zen has a non-standard LLC layout, so it probably has multiple L3s in many configurations (probably octo-core+)...
post #706 of 758
Quote:
Originally Posted by Themisseble View Post

AMD is pretty quiet about ZEN core info... they are only saying 40%+ IPC over excavator.

We know quite a bit from the public patches, though. We know the general capabilities of its ten pipelines, for example.

We have some of their papers and patents that suggest seriously low cache latencies as well (as good as Haswell, even).

We know that they are targeting "closer to 4Ghz" and 95W as well. We just don't know for which SKUs...

In fact, I think we have more information now about Zen's internals than we had for Bulldozer as this point. It wasn't until they released the optimization guide that anyone started to put the math together and realize that Bulldozer, by design, would have trouble with single threaded applications.

The great thing here, is that we have this much information... and those of us who do that math actually have a hard time figuring out how Zen will only be 40% faster than Excavator... the only explanations being that AMD went the fastest, crudest, path possible in the rest of the core in order to get a quality product to market... which would explain why they already know the next iteration will be 15% faster (itself quite a nice jump in performance).
post #707 of 758
Quote:
Originally Posted by looncraz View Post

The great thing here, is that we have this much information... and those of us who do that math actually have a hard time figuring out how Zen will only be 40% faster than Excavator

Meaning you think it will be faster?
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post #708 of 758
Quote:
Originally Posted by looncraz View Post

We know quite a bit from the public patches, though. We know the general capabilities of its ten pipelines, for example.

We have some of their papers and patents that suggest seriously low cache latencies as well (as good as Haswell, even).

We know that they are targeting "closer to 4Ghz" and 95W as well. We just don't know for which SKUs...

In fact, I think we have more information now about Zen's internals than we had for Bulldozer as this point. It wasn't until they released the optimization guide that anyone started to put the math together and realize that Bulldozer, by design, would have trouble with single threaded applications.

The great thing here, is that we have this much information... and those of us who do that math actually have a hard time figuring out how Zen will only be 40% faster than Excavator... the only explanations being that AMD went the fastest, crudest, path possible in the rest of the core in order to get a quality product to market... which would explain why they already know the next iteration will be 15% faster (itself quite a nice jump in performance).

+ 40% is no much on FPU... this shouldnt be a problem.
+ 40% for integer... well in some cases A10 7850K OC is doing quite well against older i5 3570K.

Also excavator proves to be very good on AVX2 instructions.
Any athlon x4 845 review?
Edited by Themisseble - 2/8/16 at 12:00pm
post #709 of 758
Quote:
Originally Posted by Robenger View Post

Meaning you think it will be faster?
.

No, but I think AMD's claim of 40% actually sounds reasonable, whereas many others think it is an "up to" claim... meaning that 40% may be limited to one or two specific cases.

40% seems more like a baseline of improvement, with a few specific exceptions. Faster caches, four dedicated wide-decoders, ten independently addressable pipelines, several generations worth of process improvements, inclusion of all of Excavator's power saving dynamics.... yeah, it's gonna be interesting. I would not be surprised to see more than 40%, but I'd really not be all that surprised to see 35%, either...
post #710 of 758
Quote:
Originally Posted by Themisseble View Post

+ 40% is no much on FPU... this shouldnt be a problem.
+ 40% for integer... well in some cases A10 7850K OC is doing quite well against older i5 3570K.

Also excavator proves to be very good on AVX2 instructions.
Any athlon x4 845 review?

Absolutely, Zen needs to improve more with floating point than with integer. 40% greater integer will pit Zen against Skylake, 40% faster FPU will be acceptable, but not enough to reach Ivy Bridge... which averages to Haswell IPC tongue.gif
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