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[KG/TT] AMD also rumored to be using GDDR5x on new 14nm GPUs (Updated) - Page 5

post #41 of 76
Quote:
Originally Posted by CynicalUnicorn View Post

Power consumption is proportional to both frequency and voltage. If you don't change the voltage and double the frequency, then power consumption is doubled. It increases with the square of the voltage IIRC, so we can compare:

(1.35V / 1.5V)2 * (12GHz / 7GHz) * (100%) = 139%

Now, based on how GDDR5 works, it isn't actually running at 7GHz, but rather a fourth that at 1750MHz. It's quad-pumped, allowing it to perform four operations per cycle. That doesn't really matter though, since we're just looking for a ratio and the effective memory speeds work as well. We could take πe times the effective bandwidths and it would work out the same.

What this tells us is that GDDR5X will require 40% more energy than GDDR5. I'm not familiar with the actual power consumptions of GDDR5 and HBM however, so it's difficult to tell by how much this amplifies HBM's relative efficiency. I'd guesstimate that this puts HBM at a 40+/-5W advantage over GDDR5X though, assuming your numbers are true.

Also lol at the bolded. Technically yes, they won't need additional bandwidth. But it certainly helps. It pushes the tech forward and it allows for much higher resolutions than previously possible. I mean, AMD went from the 384-bit @ 5.5GHz effective 7970 to the 4096-bit @ 1GHz effective Fury X in just two generations, doubling the memory bandwidth. Nvidia has gone from the 256-bit @ 6GHz effective 680 to the 384-bit @ 7GHz effective Titan X in two generations as well, with a smaller but still respectable 70% increase.
Who told you GDDR5X runs at 12GHz effective clocks? It is identical to GDDR5 and use quad channel as well, meaning your math is dead wrong unless I misunderstand it.
GDDR5X at 1.75GHz will probably not consume much more than GDDR5 at 1.25GHz thanks to lower voltage, meaning a 660GB/s @ 384bit bus will consume 25W more than HBM1. Reducing that memory clock down to ~1.5GHz and getting similar bandwidth as HBM1 and it should consume just as much as HBM. Effectively matching the technology in all aspects except size requirement.

I`m sure HBM2 will be replacing GDDR5X, but with the benefits over GDDR5, I dont think anyone is in a rush
Quote:
Originally Posted by mtcn77 View Post

I referenced TSMC. I think they need to hire some editors to replace their engineers.
Why have TSMC made HBM infographics? Seems like marketing for something they dont made, unless thats not from TSMC.
Just estimates anyway and actually not far away from Anandtech when I look at it again (42W-7W = 35W)
post #42 of 76
Quote:
Originally Posted by Forceman View Post

They wouldn't have had the power headroom to put as many shaders or run it as high-clocked if they had to use GDDR5, plus the extra die space they would have had to allocate to the memory controller. It would have been a less powerful card without HBM.

Oh yeah, forgot about that. Thanks for the correction. Fiji could not have existed without HBM.
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post #43 of 76
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Quote:
Originally Posted by iLeakStuff View Post

What on earth have you been smoking? Who told you GDDR5X runs at 12GHz effective clocks? It is identical to GDDR5 and use quad channel as well, meaning your math is dead wrong.
GDDR5X at 1.75GHz will probably not consume much more than GDDR5 at 1.25GHz thanks to lower voltage, meaning a 660GB/s @ 384bit bus will consume 25W more than HBM1. Reducing that memory clock down to ~1.5GHz and getting similar bandwidth as HBM1 and it should consume just as much as HBM. Effectively matching the technology in all aspects except size requirement.
Why have TSMC made HBM infographics? Seems like marketing for something they dont made, unless thats not from TSMC.
Just estimates anyway and actually not far away from Anandtech when I look at it again (42W-7W = 35W)
Math just sighed.
Quote:
Originally Posted by iLeakStuff View Post

Who told you GDDR5X runs at 12GHz effective clocks?
I suppose you never read anything about gddr5x.
Quote:
Originally Posted by iLeakStuff View Post

Why have TSMC made HBM infographics? Seems like marketing for something they dont made, unless thats not from TSMC.
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post #44 of 76
Quote:
Originally Posted by iLeakStuff View Post

What on earth have you been smoking? Who told you GDDR5X runs at 12GHz effective clocks? It is identical to GDDR5 and use quad channel as well, meaning your math is dead wrong unless I misunderstand it.

You did. You really, really did. Right now, GDDR5 manages 7Gb/s per pin. One pin can transfer one bit at once, obviously. Therefore in order to reach a bandwidth of 7Gb/s per pin, each pin would need to be clocked at 7GHz effective. GDDR5X is supposed to start off at a much higher 12Gb/s per pin. We can conclude, therefore, that GDDR5X must be running at 12GHz effective.

Memory channels are based on the memory controller; they have nothing to do with the memory itself. At least, not with DDR1/2/3/4. It might be different for the graphics variants, but I am highly skeptical.

Quote:
GDDR5X at 1.75GHz will probably not consume much more than GDDR5 at 1.25GHz thanks to lower voltage, meaning a 660GB/s @ 384bit bus will consume 25W more than HBM1. Reducing that memory clock down to ~1.5GHz and getting similar bandwidth as HBM1 and it should consume just as much as HBM. Effectively matching the technology in all aspects except size requirement.

[citation needed]




(Thanks for finding that, Mr. mtcn77!)

So. What does this tell us? GDDR5 consumes, right now, on the order of 40-50W. Let's say 50W because that's a nice number to work with and also fits the higher end estimates of 56W. As stated before, power consumption is proportional to the square of the voltage. Power consumption is also proportional to the frequency. So we run that same equation I did earlier, using GDDR5 now and GDDR5X if/when it launches:

50W * (1.35V / 1.5V)2 * (12GHz effective / 7GHz effective) = 69.4W = 70W

Again, that's the same 40% increase I claimed earlier. If Nvidia were to implement 12GHz GDDR5X into the Titan X right now without touching the memory bus, it would only reach:

(1 byte / 8 bits) * (384 bits / cycle) * (12*109 cycles / second) = 576GB/s bandwidth.

To beat HBM1 right now, GDDR5X would use five times the energy. (Based on HBM1 stacks running at 128GB/s and 3.5W each.) It simply is not feasible. It's a massive power difference. And all of this is being nice. What if I'm wrong? What if power consumption is only linear with voltage? What if it's quadratic with frequency? Now you're looking at >150% increases in power consumption. It's just not feasible. If you can find some sources for your claims, sure, I'll look into it. But until now, you've spouted some meaningless numbers with the source being, "I feel like this is how it should be." Math doesn't care about your emotions. Find data or stop arguing.

EDIT: I misread the graph. Numbers changed. Point still holds.

EDIT 2: Found the formula for CPU power consumption. It's P = C*V2*f, where C is capacitance, V is voltage, and f is frequency. I must assume this also applies to memory since they're reasonably similar - a bunch of silicon components switching states at very high frequencies. Not sure where capacitance comes into play however. I guess that's an inherent part of the CPU design, or it's affected by binning? I dunno.
Edited by CynicalUnicorn - 10/29/15 at 11:06am
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post #45 of 76
I'm pretty sure I read that the way GDDR5X increases bandwidth is by doubling the data on each clock cycle, so it wouldn't run any faster than GDDR5 (probably slower in fact).
Quote:
"In order to surpass the 8 Gbps barrier of GDDR5, without completely building a new memory technology from the ground up, Micron doubled the pre-fetch of GDDR5 from eight data words for each memory access, to 16 data words per access. Doing this resulted in 10 to 12 Gbps on the first generation, and the company expects to be able to surpass 14 Gbps, and perhaps reach 16 Gbps and beyond as the technology is refined."

Edited by Forceman - 10/29/15 at 10:51am
post #46 of 76
Quote:
Originally Posted by GHADthc View Post

'
Mmm looks like Micron rained on both Hynix and Samsungs parade eh?

When I think about Fiji, I am getting flashbacks of the HD2900 with its GDDR3 and 512-Bit bus width...and now HBM1 will probably never be used again even for lower end cards, due to GDDR5X being on the scene.

If Micron rained on Hynix and Samsung's HBM parade, how do you propose AMD stick GDDR on an interposer? AMD didn't just plop HBM on an enthusiast class GPU, but they have developed working technology already on the market that enables it's use, such as interposers and TSVs. These technologies enable new products like high performance APUs for HPC for example. Nobody is raining on anyone's parade in any way shape or form, as HBM is a necessary technology, AMD is just leading the industry in that development. Like they did with other memory technologies. I think those flashbacks must be more like hallucinations, because Fiji is nothing like what you propose. How can it be when it is trading blows with it's competition's top card with a similar power draw? Does the competition have anything in the same class as an HBM enabled R9 Nano?
Edited by flippin_waffles - 10/29/15 at 10:56am
post #47 of 76
I also think hbm is best equipped to 'win' in the future, cant wait to see a cpu using it, I think sony will first on a new console or maybe nintendo smile.gif I think the same non scalability applies to gddr as ddr
http://www.extremetech.com/computing/197720-beyond-ddr4-understand-the-differences-between-wide-io-hbm-and-hybrid-memory-cube/2
post #48 of 76
Quote:
Originally Posted by criminal View Post

Oh yeah, forgot about that. Thanks for the correction. Fiji could not have existed without HBM.

Well I don't think it's impossible...

Other than cost, what's to stop a GPU manufacturer from shipping a GPU with it's own power brick?
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post #49 of 76
Power brick? What do you mean?
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post #50 of 76
Quote:
Originally Posted by CynicalUnicorn View Post

Power brick? What do you mean?

laptop_adapter.jpg

IIRC a graphics card used in in the past, like around 2006
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