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[Various] Intel's new Xeon E5-2602 V4 CPU to sport a whopping 5.1GHz clockspeed and 165W TDP - Page 8

post #71 of 102
Quote:
Originally Posted by epic1337 View Post

more or less yeah, at 661mm² so long as they keep the power density below 0.7W per mm² ( <450W TDP ) and it'll remain somewhat cool with the right cooling solution.

BUT, you have to remember these are server chips, if you fit one of that on a U1 or U2 case it'll overheat with a low-profile heatsink.
its like expecting a NH-L9 to cool a 5Ghz i7-4790K, which is very much impossible.




and, these massive core arrays aren't meant for high clocks, most of their usage is on raw compute where clock speed doesn't really matter.
now if you argue that they could just use bigger coolers, or liquid coolers, that beats their intended use in high-density arrays, these chips are used by the dozens on a single rack.

Clocks do matter. . but they're low for a reason.. to 'lower' the probability of calculation errors/anomalies.. All these g4m3r 1337 overclocked hardware are actually completely unstable in the eyes of the 'people who do real work'.. hahahaha..

Who cares if a 3d cube is rendered slightly ajar in your vidya..

But let's say you build a bridge, and a decimal place was off because 1 error got factored 100 times throughout the length of the bridge. Bridge falls down.. and it wasn't godzilla's fault.
post #72 of 102
Quote:
Originally Posted by tp4tissue View Post

Clocks do matter. . but they're low for a reason.. to 'lower' the probability of calculation errors/anomalies.. All these g4m3r 1337 overclocked hardware are actually completely unstable in the eyes of the 'people who do real work'.. hahahaha..

Who cares if a 3d cube is rendered slightly ajar in your vidya..

But let's say you build a bridge, and a decimal place was off because 1 error got factored 100 times throughout the length of the bridge. Bridge falls down.. and it wasn't godzilla's fault.

you've just pointed out why it doesn't matter, high clocks isn't worth it for their intended use.
post #73 of 102
Quote:
Originally Posted by epic1337 View Post

you have to understand one thing, the contact area of the die itself dictates the overall efficiency of the heat transfer.
it does not matter if you put in a 360mm CLC or a 80mm CLC, the die's surface area is still much smaller.
you can actually measure this by taking the water temp and comparing it to the die temp.
if the water isn't hot to begin with then whats there for the rads to cool?


now we've got another issue, if you cram more power on a tinnier chip, of course it'll end up becoming hotter.
CPU dies are much, much more smaller.
i7-4970K = 177mm²
GTX980Ti = 601mm²

Haswell die map

Look at where the actual CPU cores are and note their size relative to the die. It's even worse than the numbers would have you believe, since the CPU cores literally take up less than 50% of the total die space, so thermal density is even higher.
post #74 of 102
Quote:
Originally Posted by magnek View Post

Haswell die map

Look at where the actual CPU cores are and note their size relative to the die. It's even worse than the numbers would have you believe, since the CPU cores literally take up less than 50% of the total die space, so thermal density is even higher.

the higher SKU server chips doesn't have an IGP.
this makes the CPU about 60%~70% of the total die size and has a good distribution, with the remainder being the IMC and QPI.

this is an 18core Haswell-EP E5 Xeon.

Edited by epic1337 - 2/1/16 at 4:50pm
post #75 of 102
Quote:
Originally Posted by tp4tissue View Post

Clocks do matter. . but they're low for a reason.. to 'lower' the probability of calculation errors/anomalies.. All these g4m3r 1337 overclocked hardware are actually completely unstable in the eyes of the 'people who do real work'.. hahahaha..

Who cares if a 3d cube is rendered slightly ajar in your vidya..

But let's say you build a bridge, and a decimal place was off because 1 error got factored 100 times throughout the length of the bridge. Bridge falls down.. and it wasn't godzilla's fault.
When you are overclocking, you are doing perfect stability. And when you are using these programs, these programs have additional checks.

I used 7 years overclocked E7200 and I had zero errors even without ECC. (And it was CPU that came with strange sticker on a box that said, never use more than 1.25V.) Still wondering what was that for. It was original Intel's packaging.

A bridge might be computed properly, but when they would hire a poor physically disabled to do that job, and who would hate that job because he/she didn't have money for school, it would fall apart because of build quality, even when he/she will not sabotage on purpose. So I guess that was a bad example. People in medieval ages didn't have PCs, but theirs bridges and castes lasted anyway.



That 5.1 GHz might be just a marketing attempt. When you see that 5.1GHz Broadwell, would you think BW-E would be decent overclocker?
post #76 of 102
Quote:
Originally Posted by epic1337 View Post

the higher SKU server chips doesn't have an IGP.
this makes the CPU about 60%~70% of the total die size and has a good distribution, with the remainder being the IMC and QPI.

this is an 18core Haswell-EP E5 Xeon.

Oh yeah I should've specified my comment was in regards to 4790K (as well as the non-HEDT chips). The high end Xeon/HEDT chips cut out the IGP, and in addition use a soldered IHS, so the power distribution is more evenly spread out and not quite as bad.
post #77 of 102
Quote:
Originally Posted by tp4tissue View Post

Clocks do matter. . but they're low for a reason.. to 'lower' the probability of calculation errors/anomalies.. All these g4m3r 1337 overclocked hardware are actually completely unstable in the eyes of the 'people who do real work'.. hahahaha..

Who cares if a 3d cube is rendered slightly ajar in your vidya..

But let's say you build a bridge, and a decimal place was off because 1 error got factored 100 times throughout the length of the bridge. Bridge falls down.. and it wasn't godzilla's fault.

What I was saying is that if the top SKU were unlocked, it would satisfy the needs of those who require the extra performance and are using the chip in non-critical scenarios. The same SKU could serve both the needs if the server user and the high end user. Also, there is room for a 250-300W TDP version of the chip that is fully validated at those clocks that would generate such a high TDP and that such a chip could be properly cooled by the solutions available today.

While I hope their stance changes in the future, currently Intel refuses to provide either.
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post #78 of 102
165W quad core.........wow
post #79 of 102
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Originally Posted by escksu View Post

165W quad core.........wow

oc'd 4790k's can hit 300w with synthetics at non-lethal voltages but usually run around 150-200w under standard loads (like x264 encoding under 1.35 - 1.4v)
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post #80 of 102
Quote:
Originally Posted by Cyro999 View Post

oc'd 4790k's can hit 300w with synthetics at non-lethal voltages but usually run around 150-200w under standard loads (like x264 encoding under 1.35 - 1.4v)

Yeah, but I just find it hard to accept the fact that we are going towards low power CPUs these days and Intel suddenly come out with a 165W monster. Remember the days when we were laughing at AMD's FX-9590 for its ridiculous TDP? Now Intel is doing the same?
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Overclock.net › Forums › Industry News › Rumors and Unconfirmed Articles › [Various] Intel's new Xeon E5-2602 V4 CPU to sport a whopping 5.1GHz clockspeed and 165W TDP