Originally Posted by prjindigo
Oh, the 970 accessing 3.8gb of the 3.5gb of ram it was given was pretty much a dead give-away in the end.
No clue what you're trying to say here.
You do understand the term "array" right? That data takes a shape in memory and there are efficient and inefficient ways to handle said data?
You do understand what I said in my post, right? There are twelve 32-bit wide memory channels on the 980 Ti mapped to twelve 512 MB memory chips and a fully intact 3 MBs of L2 cache. It's a uniform 1:1 ratio which means the 980 Ti accesses all of its 6 GBs of VRAM at full speed with no XOR contention issues like the 970.
That the whole point of HBM/HBM2 is changing the way the data is handled into a symmetrical form on the card? That this results in nV needing to change away from their 384 bus system...
No, the whole point of HBM is to continue increasing bandwidth while simultaneously decreasing power consumption. It has the added benefits of increased memory density, reduced latency, and reduced PCB complexity. There is nothing fundamentally wrong with GDDR5's ability to handle data. If there was, GDDR5 would be a fundamentally broken memory technology that would have never gained traction and it would mean all GDDR5-equipped cards (both AMD and Nvidia) have memory issues.
As to you're singling out of Nvidia's 384-bit memory buses, there's nothing asymmetrical about them. I've addressed this already. 1:1 mapping of memory chips to memory channels and all. Considering your original post on the subject mistakenly stated that 8 GBs would be the proper fit for a 384-bit bus, despite chips of the size necessary to do so not existing, it's clear that you don't understand GPU memory subsystems. Please, read up on the subject before insisting on false information.Edited by Serandur - 1/22/16 at 10:22pm