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[OC3D] AMD's Zen will have a "greater than 40%" IPC improvement over Excavator, says Lisa Su - Page 45

post #441 of 841
MOAR IPC.
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post #442 of 841
Quote:
Originally Posted by The Stilt View Post

AM4 is dual channel DDR4. Eight channels mean four die MCM package.

All Zen processors are SoCs with on chip controllers, they can modify the architecture at their leisure.
post #443 of 841
Quote:
Originally Posted by FallenFaux View Post

I wouldn't be surprised if we see 16c 4-channel memory on the AM4 socket and then 32c 8-channel memory on a G34 replacement.

I would as the platform cost would then skyrocket with little to no gain for the majority of use cases.

That said, it would make their APUs drastically better - and AMD has already said they have no intention of aiming for the bottom end of the market any more. Which is a good thing. Quad channel DDR4 on AM4 would be a beautiful thing, especially if AMD allowed some boards to have it and others to not - so that low end motherboards would not have it.

Still, it's highly unlikely. I think sideband memory on the APUs are more likely.
post #444 of 841
Quote:
Originally Posted by Fyrwulf View Post

All Zen processors are SoCs with on chip controllers, they can modify the architecture at their leisure.

To do that AMD would need to make new masks for said chips costing them a good amount of money. I wonder if AMD is pulling another Kaveri like deal where there are actually 4 memory controllers on die but they only enabled 2 for consumer chips? Just a wild idea...
post #445 of 841
Quote:
Originally Posted by Fyrwulf View Post

All Zen processors are SoCs with on chip controllers, they can modify the architecture at their leisure.

Not really. Zen CPUs (17h 00-0Fh) are not SoCs. Raven Ridge is the first Zen based SoC part.

In AMDs financial situation they cannot afford making several different designs. That´s why they will use harvesting and MCM to make different products for different purposes and markets. In the exactly same manner as with Bulldozer.
post #446 of 841
Quote:
Originally Posted by The Stilt View Post

Not really. Zen CPUs (17h 00-0Fh) are not SoCs. Raven Ridge is the first Zen based SoC part.

In AMDs financial situation they cannot afford making several different designs. That´s why they will use harvesting and MCM to make different products for different purposes and markets. In the exactly same manner as with Bulldozer.

So what you're saying is that AMD is lying. There are shipping manifests that show APUs test parts with different controllers for low and mid range parts. I suppose AMD is lying to Indian customs, then?
post #447 of 841
Quote:
Originally Posted by Fyrwulf View Post

So what you're saying is that AMD is lying. There are shipping manifests that show APUs test parts with different controllers for low and mid range parts. I suppose AMD is lying to Indian customs, then?

Where?
post #448 of 841
Not sure if this is old news, but I'll post anyway... Source: http://techfrag.com/2016/02/12/amd-zen-high-end-exascale-cpu-and-apu-specs-leaked/
Can someone extrapolate with this info? How does it compare to Intel?
Quote:
AMD Zen High End ‘Exascale’ CPU, 1-4 Socket (1P-4P) – Specs As Per CERN
  • 32 ZEN x86 Core, 6-wide
  • 12 8KB L0 Cache (4KB per core)
  • 2 MB L1 D-Cache (64KB per core)
  • 2 MB L1 I-Cache (64 KB per core)
  • 16 MB L2 Cache (512 KB per core)
  • 64? MB L3 Cache (8MB cluster per quad unit)
  • 576-bit Memory Controller (8×72-bit, 64-bit + 8-bit ECC)
  • 204.8 GB/s via DDR4-3200 (ECC Off)
  • 170.6 GB/s via DDR4-2666 (ECC On)


AMD Zen High End Exascale APU, 1-2 Socket (1P-2P) – Specs From Fast Forward
  • 16 ZEN x86 Core, 6-wide
  • 64 KB L0 Cache (4KB per core)
  • 1 MB L1 D-Cache (64KB per core)
  • 1 MB L1 I-Cache (64 KB per core)
  • 8 MB L2 Cache (512 KB per core)
  • No L3 Cache
  • 288-bit CPU Memory Controller (4×72-bit, 64-bit + 8-bit ECC)
  • 102.4 GB/s via DDR4-3200 (ECC Off)
  • 85.3 GB/s via DDR4-2666 (ECC On)
  • 102.4 GB/s between CPU and GPU via GMI
  • ~2000-core Polaris GPU
  • 2048-bit GPU Memory Controller
  • 8 GB HBM2 SGRAM Memory (2 chips at 4GB)
  • 512 GB/s GPU Bandwidth
post #449 of 841
Quote:
Originally Posted by Cyrious View Post

Octo-channel DDR4? Goddamn. Wiring that up is going to be interesting.

And since its likely going to be dual-16c CPUs in a single package, what are the odds AMD will have a high end 16C SKU for the consumer side?

Since it's just two 16 core Zen CPUs on one die, it probably just has two quad channel DDR4 controllers. The two CPUs are probably connected via AMD's new coherent data fabric technology.
Edited by variant - 2/12/16 at 6:13pm
post #450 of 841
lolk
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Overclock.net › Forums › Industry News › Hardware News › [OC3D] AMD's Zen will have a "greater than 40%" IPC improvement over Excavator, says Lisa Su