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[OC3D] AMD's Zen will have a "greater than 40%" IPC improvement over Excavator, says Lisa Su - Page 46

post #451 of 841
Quote:
Originally Posted by Dom-inator View Post

Not sure if this is old news, but I'll post anyway... Source: http://techfrag.com/2016/02/12/amd-zen-high-end-exascale-cpu-and-apu-specs-leaked/
Can someone extrapolate with this info? How does it compare to Intel?

With the information we have now, it's not really possible to make a very good comparison (we need clock speeds and performance profiles to make a good educated guess), but here's my amateur analysis from what I can remember right now:


According to the ARK, Intel's current best Haswell-EX E7 (E7-8890v3) is an 18-core/36-thread at 2.5/3.3Ghz [1]. If Zen's IPC is roughly equal (as we pretty much expect it to be), that 32-core/64-thread would theoretically match it at less than 2Ghz in heavily threaded workloads. Both support up to 4 CPUs per motherboard. IIRC, Broadwell-EX is going to have up to 22 cores, but I don't think it's known how it will clock either, so comparing them isn't really possible right now.


The 16-core APU is likely targeting a different market than the Xeons. The lack of L3 cache would probably hurt its performance in server workloads, and the iGP would be a waste of a whole lot of die space unless you're using HSA (and I'm not sure any server workloads can use that right now). On HPC, on the other hand...

Well, a ~2000 SP Polaris GPU with effectively unlimited memory bandwidth would be pretty beastly. Extrapolating from Hawaii and Tonga, it could hit 4+ TFLOPS single precision and (depending on how it's set up) up to 2+ TFLOPS dual precision [2]. At that point, it'd roughly match the FirePro W8100; against NV, it'd compete against the Quadro M5000 in SP and beat every current Quadro/Tesla in DP (and by an order of magnitude, at that) [3]. How it'd actually perform depends on the workload and how Polaris/GCN 4 is different than GCN 3. Factor in HSA, and this could be the dream system for high-end HPC; it seems that AMD really wants to take back some marketshare from the Teslas and Xeon Phis.


[1] E7-8890 v3 on the ARK

[2] AMD FirePro Wx100 series

[3] Nvidia Quadro Mxxx series
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post #452 of 841
Does this support Optane?
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post #453 of 841
Quote:
Originally Posted by The Stilt View Post

Where?

http://wccftech.com/amd-am4-cpu-apu-motherboard/

Admittedly, I got my links mixed up. Still, it makes no sense that AMD would revert to off-chip memory controllers when it hasn't done that since the 990FX platform, as off-chip controllers are strictly inferior and actually incur additional financial burdens, especially considering that they'd have to relearn how to design off-chip controllers as opposed to the integrated SoCs they've done since the APUs came out. And anyway, they have to create new masks for every chip, so your objection on that front doesn't hold up. Or, you know, the fact that they're using groups of four cores as building blocks seems to suggest that they're all going to utilize SoC architecture. Oh, how about the unified socket itself?

Basically, you're just flat out wrong.
post #454 of 841
Quote:
Originally Posted by czin125 View Post

Does this support Optane?

Unless Intel actually pushes for it to be an industry standard, which is always possible, I don't see AMD adopting it. And so far Optane is vaporware, with the last mention of it being a flurry of press releases in November of last year.
post #455 of 841
Quote:
Originally Posted by Serious_Don View Post

In before your PM inbox is full within 30 seconds. biggrin.gif
Quote:
Originally Posted by Fyrwulf View Post

http://wccftech.com/amd-am4-cpu-apu-motherboard/

Admittedly, I got my links mixed up. Still, it makes no sense that AMD would revert to off-chip memory controllers when it hasn't done that since the 990FX platform, as off-chip controllers are strictly inferior and actually incur additional financial burdens, especially considering that they'd have to relearn how to design off-chip controllers as opposed to the integrated SoCs they've done since the APUs came out. And anyway, they have to create new masks for every chip, so your objection on that front doesn't hold up. Or, you know, the fact that they're using groups of four cores as building blocks seems to suggest that they're all going to utilize SoC architecture. Oh, how about the unified socket itself?

Basically, you're just flat out wrong.
Yes, ive read from a different source that bar a display controller, zen cpu is a full soc
post #456 of 841
Quote:
Originally Posted by Fyrwulf View Post

http://wccftech.com/amd-am4-cpu-apu-motherboard/

Admittedly, I got my links mixed up. Still, it makes no sense that AMD would revert to off-chip memory controllers when it hasn't done that since the 990FX platform, as off-chip controllers are strictly inferior and actually incur additional financial burdens, especially considering that they'd have to relearn how to design off-chip controllers as opposed to the integrated SoCs they've done since the APUs came out. And anyway, they have to create new masks for every chip, so your objection on that front doesn't hold up. Or, you know, the fact that they're using groups of four cores as building blocks seems to suggest that they're all going to utilize SoC architecture. Oh, how about the unified socket itself?

Basically, you're just flat out wrong.

What off-chip memory controllers you are talking about? Off course they are not off-chip rolleyes.gif

Zen will have two memory channels per die and the server platform will use multiple dies per package (MCM). In order to have 32 cores and eight memory channels per processor, four dies will be used. AM4 is will use single die per package, same as all the previous desktop designs have.

Also, those AM4 parts in Zauba are AM4 Bristol Ridge (Excavator) parts rolleyessmileyanim.gif
post #457 of 841
Quote:
Originally Posted by The Stilt View Post

What off-chip memory controllers you are talking about? Off course they are not off-chip rolleyes.gif

Zen will have two memory channels per die and the server platform will use multiple dies per package (MCM). In order to have 32 cores and eight memory channels per processor, four dies will be used. AM4 is will use single die per package, same as all the previous desktop designs have.

Also, those AM4 parts in Zauba are AM4 Bristol Ridge (Excavator) parts rolleyessmileyanim.gif


Hey, Lucy, no moving the goalposts. I stated categorically that all Zen units will be SoCs, which in AMD parlance means all former Northbridge and Southbridge functions are on-die and that this gave them the freedom to tailor what memory is supported within an SKU. You denied that and claimed AM4 will strictly use dual channel DDR4, which implies that any motherboard will have a physical Northbridge chip. It's irrelevant that those parts are Bristol Ridge, the consumer and Pro lines will use different memory, and indeed will support different max speeds, but the same socket. My point is proven, yours is disproven.
post #458 of 841


Really? New AM3+/FM2+ mobos coming? FOR WHAT? Just let it be like it is until Zen/Bristol and be done with it.
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post #459 of 841
Quote:
Originally Posted by MadRabbit View Post



Really? New AM3+/FM2+ mobos coming? FOR WHAT? Just let it be like it is until Zen/Bristol and be done with it.

They have to keep the platform fresh, believe it or not... and, of course, Carrizo is being released for FM2+ as well as AM4, so that's pretty awesome (I have a FM2+ system for my HTPC, Carrizo options may be quite nice to have - along with a nice, low power, Polaris GPU).

Zen is also the better part of a year away...

I am surprised by AM3+ getting some new life, though. Maybe AMD is going to try to win some love and package Carrizo in FX-form? I would be really surprised... I'm going to have to do some more BIOS digging (Carrizo for FM3+ confirmed that way).
post #460 of 841
Quote:
Originally Posted by Fyrwulf View Post

Hey, Lucy, no moving the goalposts. I stated categorically that all Zen units will be SoCs, which in AMD parlance means all former Northbridge and Southbridge functions are on-die and that this gave them the freedom to tailor what memory is supported within an SKU. You denied that and claimed AM4 will strictly use dual channel DDR4, which implies that any motherboard will have a physical Northbridge chip. It's irrelevant that those parts are Bristol Ridge, the consumer and Pro lines will use different memory, and indeed will support different max speeds, but the same socket. My point is proven, yours is disproven.

What are you talking about?

Just like all AMD CPUs since K8, Zen has integrated memory controller. The memory controller in Zen supports dual channel DDR4. In order to have 32 cores and eight memory channels per processor, four dies will be used in the same package (MCM config). The topology is no different to current Bulldozer server parts where two Orochi dies were attached on the same substrate (Opteron 6K series). Opteron 6K series parts have 16 cores and support quad channel DDR despite each of the dies have just eight cores and dual channel memory controller each.

SoC = CPU, GPU, FCH/PCH (System on a Chip).

Since Zen CPUs will have no integrated GPU and the FCH / PCH is external, what makes it a SoC? Raven Ridge is a SoC, while Summit Ridge is not.
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