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[OC3D] AMD's Zen will have a "greater than 40%" IPC improvement over Excavator, says Lisa Su - Page 49

post #481 of 841
Quote:
Originally Posted by The Stilt View Post

Unless AMD will make a separate design to be used only in server parts, each Zen die has up to eight cores and dual channel memory. This has been stated in the roadmaps also. They didn´t do this even when they were financially in much better condition (2011), so why do you expect they will do it now when they are at the edge of bankruptcy? MCM is a no-brainer especially when they are replacing the socket at the same time (socket could be designed to physically fit many separate dies).

The 32-core version was confirmed by a CERN engineer to be a 2x 16 core MCM config with an "improved" interconnection and quad channel controllers. http://hothardware.com/news/cern-engineer-leaks-amd-zen-architecture-details-claiming-40-percent-increase-in-ipc-up-to-32-cores

Have we ever seen a 4x MCM config from Intel or AMD? That'd be a bad choice. It could be that the 8 core versions have a dual-channel ddr controller, that's cool but AMD using a quad channel controller for their 16 core versions has little to do with how close they are to bankruptcy.
post #482 of 841
Ok, I guess they made two separate designs then. Would be interesting to know if those 16 core designs are actually two smaller dies put on the same piece of silicon, or is there other differences in the design.

A rumor says AM4 is a PGA package with 1331 pins on it. The CPU itself is supposed to be exactly the same size (40x40mm substrate) as all AMD desktop CPUs have been since Socket 754. The pin size and pitch is just smaller and tighter than on previous CPUs wink.gif
post #483 of 841
Quote:
Originally Posted by Cyrious View Post

Is that from an official slide or is that just Fud's crap?



I know about as much as you...
post #484 of 841
Quote:
Originally Posted by DarkBlade6 View Post

Holy s***
A big ass Integrated GPU, 16 cores, HBM stack (for the IGP, I presume) plus an additionnal quad channel DDR4 memory controller all on the same DIE?!!! That's just freakin impossible.... well atleast not for the consumer market biggrin.gif

For the server or HPC markets, AMD could probably earn a hefty margin on a product like this that would make it worthwhile even with ~50% or lower yields. Not to mention just how much harvesting they can do with something so massive.

You can cut a 16-core die down to 10 cores and quite possibly break even on the sale (which is better than losing the die entirely). The HBM, of course, is on a 2048-bit bus, which means two HBM2 stacks.

Honestly, if they were to do this, I would not be surprised, at all, if the graphics and peripheral support were all on separate dies on an interposer or MCM. That could greatly increase yield... but it seems like we would have seen some hint of that by now from other sources.
post #485 of 841
Quote:
Originally Posted by looncraz View Post



I know about as much as you...
Alright then, lets assume its Fud's crap for now, as I dont see it fitting in with AMD's past designs of the large Stars and Construction cores (cores on either side of the NB, with a memory controller at one end and HTs ringing the other 3 sides of the die.). Going with a "Straight 4" setup with the L3 cache facing inwards would end up having the L3 segments all closer together and directly linked to the NB. There could be a small gap between the core clusters on the sides of the chip allowing access to the memory controllers, with IO/HT links at each end of the die.

Basically think of it as a Thuban die with a dual channel memory controller on each of the long sides (4 channels total), IO on the ends, and 4 clusters of intel-style cores w/ the L3 facing inwards.
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post #486 of 841
Quote:
Originally Posted by Fyrwulf View Post

http://wccftech.com/amd-am4-cpu-apu-motherboard/

Admittedly, I got my links mixed up. Still, it makes no sense that AMD would revert to off-chip memory controllers when it hasn't done that since the 990FX platform, as off-chip controllers are strictly inferior and actually incur additional financial burdens, especially considering that they'd have to relearn how to design off-chip controllers as opposed to the integrated SoCs they've done since the APUs came out. And anyway, they have to create new masks for every chip, so your objection on that front doesn't hold up. Or, you know, the fact that they're using groups of four cores as building blocks seems to suggest that they're all going to utilize SoC architecture. Oh, how about the unified socket itself?

Basically, you're just flat out wrong.

When did he ever say AMD was using off-chip memory controllers? If anything you came closest to saying that with your "modular memory controller can be socketed in to different configurations" thing. AMD didnt even use off chip memory controllers even in 990FX. I just don't even know how you come to these absurd ideas in your head.

Quote:
Originally Posted by Fyrwulf View Post

Hey, Lucy, no moving the goalposts. I stated categorically that all Zen units will be SoCs, which in AMD parlance means all former Northbridge and Southbridge functions are on-die and that this gave them the freedom to tailor what memory is supported within an SKU. You denied that and claimed AM4 will strictly use dual channel DDR4, which implies that any motherboard will have a physical Northbridge chip.

dude........ Just, don't even talk about processors anymore. You obviously have no real understanding of them whatsoever.
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post #487 of 841
ZEN High End ‘Exascale’ CPU, 1-4 Socket (1P-4P) – Specs As Per CERN

32 ZEN x86 Core, 6-wide
12 8KB L0 Cache (4KB per core)
2 MB L1 D-Cache (64KB per core)
2 MB L1 I-Cache (64 KB per core)
16 MB L2 Cache (512 KB per core)
64? MB L3 Cache (8MB cluster per quad unit)
576-bit Memory Controller (8×72-bit, 64-bit + 8-bit ECC)
204.8 GB/s via DDR4-3200 (ECC Off)
170.6 GB/s via DDR4-2666 (ECC On)

ZEN High End Exascale APU, 1-2 Socket (1P-2P) – Rumored Specs From Fast Forward

16 ZEN x86 Core, 6-wide
64 KB L0 Cache (4KB per core)
1 MB L1 D-Cache (64KB per core)
1 MB L1 I-Cache (64 KB per core)
8 MB L2 Cache (512 KB per core)
No L3 Cache
288-bit CPU Memory Controller (4×72-bit, 64-bit + 8-bit ECC)
102.4 GB/s via DDR4-3200 (ECC Off)
85.3 GB/s via DDR4-2666 (ECC On)
102.4 GB/s between CPU and GPU via GMI
~2000-core Polaris GPU
2048-bit GPU Memory Controller
8 GB HBM2 SGRAM Memory (2 chips at 4GB)
512 GB/s GPU Bandwidth

http://vrworld.com/2016/02/12/cern-confirms-amd-zen-high-end-specifications/
post #488 of 841
Quote:
Originally Posted by Pro3ootector View Post

ZEN High End ‘Exascale’ CPU, 1-4 Socket (1P-4P) – Specs As Per CERN

32 ZEN x86 Core, 6-wide
12 8KB L0 Cache (4KB per core)
2 MB L1 D-Cache (64KB per core)
2 MB L1 I-Cache (64 KB per core)
16 MB L2 Cache (512 KB per core)
64? MB L3 Cache (8MB cluster per quad unit)
576-bit Memory Controller (8×72-bit, 64-bit + 8-bit ECC)
204.8 GB/s via DDR4-3200 (ECC Off)
170.6 GB/s via DDR4-2666 (ECC On)

ZEN High End Exascale APU, 1-2 Socket (1P-2P) – Rumored Specs From Fast Forward

16 ZEN x86 Core, 6-wide
64 KB L0 Cache (4KB per core)
1 MB L1 D-Cache (64KB per core)
1 MB L1 I-Cache (64 KB per core)
8 MB L2 Cache (512 KB per core)
No L3 Cache
288-bit CPU Memory Controller (4×72-bit, 64-bit + 8-bit ECC)
102.4 GB/s via DDR4-3200 (ECC Off)
85.3 GB/s via DDR4-2666 (ECC On)
102.4 GB/s between CPU and GPU via GMI
~2000-core Polaris GPU
2048-bit GPU Memory Controller
8 GB HBM2 SGRAM Memory (2 chips at 4GB)
512 GB/s GPU Bandwidth

http://vrworld.com/2016/02/12/cern-confirms-amd-zen-high-end-specifications/

My question with this is why the hell would they disable L3 cache on the APU chip? Are they using the HBM for it? Or is it something else?
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post #489 of 841
Quote:
Originally Posted by Cyrious View Post

My question with this is why the hell would they disable L3 cache on the APU chip? Are they using the HBM for it? Or is it something else?
isnt it a die space issue? The iGPU takes up too much space to fit L3.
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post #490 of 841
Quote:
Originally Posted by 7850K View Post

isnt it a die space issue? The iGPU takes up too much space to fit L3.

It could be as a means to save die space, but this is a chop clearly targeted at the very segment which most benefits from L3 caches... so it would be an unusual choice. It would seriously make more sense to just use an on-package GPU with a custom bus rather than an APU if they had to make such a trade. Then again, we don't really know how Zen will behave without an L3, either. AMD may well want to find out on a chip that will have significant enough margin to pay for itself.
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