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[OC3D] AMD's Zen will have a "greater than 40%" IPC improvement over Excavator, says Lisa Su - Page 50

post #491 of 841
Quote:
I easily see a 100W 8c/16t CPU on 14nm finfet being possible.

You can make a 6700k consume 50w (or substantally less), just not at the types of voltages typically used on OCN. Fairly easy to double that up to 8c16t 100w
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post #492 of 841
Quote:
Originally Posted by Pro3ootector View Post


ZEN High End Exascale APU, 1-2 Socket (1P-2P) – Rumored Specs From Fast Forward

16 ZEN x86 Core, 6-wide
64 KB L0 Cache (4KB per core)
1 MB L1 D-Cache (64KB per core)
1 MB L1 I-Cache (64 KB per core)
8 MB L2 Cache (512 KB per core)
No L3 Cache
288-bit CPU Memory Controller (4×72-bit, 64-bit + 8-bit ECC)
102.4 GB/s via DDR4-3200 (ECC Off)
85.3 GB/s via DDR4-2666 (ECC On)
102.4 GB/s between CPU and GPU via GMI
~2000-core Polaris GPU
2048-bit GPU Memory Controller
8 GB HBM2 SGRAM Memory (2 chips at 4GB)
512 GB/s GPU Bandwidth

http://vrworld.com/2016/02/12/cern-confirms-amd-zen-high-end-specifications/


with a core count equal to a 380x, an igpu like that would be pretty ridiculous. even cutting it in half would be ludicrous(R7-370X core count)
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post #493 of 841
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Originally Posted by EniGma1987 View Post

dude........ Just, don't even talk about processors anymore. You obviously have no real understanding of them whatsoever.

I'll do as I please. You don't like it, get screwed.
post #494 of 841
Quote:
Originally Posted by 7850K View Post

isnt it a die space issue? The iGPU takes up too much space to fit L3.
Except these chips are very very likely to be MCMs, with everything that isnt the GPU or HBM on the Zen die. If the list of specs is correct, the Zen dies used in each one are exactly the same, just that one has 2 dies and the other has one that shares with an IGPU and HBM stacks.

Its why it doesnt make sense at all. Its the same friggin base die, so why not leave L3 activated?
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post #495 of 841
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Originally Posted by Cyrious View Post

Except these chips are very very likely to be MCMs, with everything that isnt the GPU or HBM on the Zen die. If the list of specs is correct, the Zen dies used in each one are exactly the same, just that one has 2 dies and the other has one that shares with an IGPU and HBM stacks.

Its why it doesnt make sense at all. Its the same friggin base die, so why not leave L3 activated?

Crazy thought, but what if the HBM is acting as an L3 cache?
post #496 of 841
Quote:
Originally Posted by Fyrwulf View Post

Crazy thought, but what if the HBM is acting as an L3 cache?
Latency would be too high IMHO. A hit there would have to leave the CPU die, travel through the interconnects, onto the GPU die, then through its memory controller, into the HBM stack (which, unless they've fixed it, will have similar latency issues as HBM1), then all the way back. It would be suitable as an L4 cache that the GPU can also use, but not as an L3.
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post #497 of 841
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Originally Posted by Fyrwulf View Post

Crazy thought, but what if the HBM is acting as an L3 cache?

Latency.
HBM might replace system ram.
Specially APU with HBM2 (quad core, 15-20GCN cores, 8-16GB HBM) all that in a single chip. It could cost around 700-1000$. = smallest form factor, most efficient PC.
post #498 of 841
Quote:
Originally Posted by Cyrious View Post

Latency would be too high IMHO. A hit there would have to leave the CPU die, travel through the interconnects, onto the GPU die, then through its memory controller, into the HBM stack (which, unless they've fixed it, will have similar latency issues as HBM1), then all the way back. It would be suitable as an L4 cache that the GPU can also use, but not as an L3.

Would it, though? You're thinking of this arrangement like you would a tower desktop with a discrete graphics card. If the HBM's on the die, then there's really nothing stopping the CPU from using the HBM directly.
post #499 of 841
Quote:
Originally Posted by Fyrwulf View Post

Would it, though? You're thinking of this arrangement like you would a tower desktop with a discrete graphics card. If the HBM's on the die, then there's really nothing stopping the CPU from using the HBM directly.
Except there would still be a significant latency penalty for using the HBM, which is attached to the iGPU as thats the only way it would get maximum bandwidth out of it for said iGPU. Cache operations for the CPU would cut performance to the GPU. On top of that, the very nature of DRAM, which is what HBM is, means that it is higher latency vs SRAM, which is what most L3 caches are.

Hell, Intel's L3 implementation on their high end Haswell-EX chips has to be split into 2 blocks with a buffer between them to keep the contention to a minimum, and that incurs enough latency that each cluster of 9 cores on each side of the die and their associated L3$ and memory controller can be treated by software as a 2P system (NUMA). Now imagine going off die to another chip and through that chip to a memory technology that is higher latency than SRAM, and then cranking it back to the CPU.
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post #500 of 841
Quote:
Originally Posted by Pro3ootector View Post

ZEN High End ‘Exascale’ CPU, 1-4 Socket (1P-4P) – Specs As Per CERN

32 ZEN x86 Core, 6-wide
12 8KB L0 Cache (4KB per core)
2 MB L1 D-Cache (64KB per core)
2 MB L1 I-Cache (64 KB per core)
16 MB L2 Cache (512 KB per core)
64? MB L3 Cache (8MB cluster per quad unit)
576-bit Memory Controller (8×72-bit, 64-bit + 8-bit ECC)
204.8 GB/s via DDR4-3200 (ECC Off)
170.6 GB/s via DDR4-2666 (ECC On)

http://vrworld.com/2016/02/12/cern-confirms-amd-zen-high-end-specifications/

Is this the Flagship Zen FX CPU or the Flagship Zen Opteron?
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Overclock.net › Forums › Industry News › Hardware News › [OC3D] AMD's Zen will have a "greater than 40%" IPC improvement over Excavator, says Lisa Su