Originally Posted by Petykemano
Do you see already points of possible improvements of zen? Bottlenecks that zen+ would fix?
Do you think that Amd with zen will soon hit a performance wall just like intel is said to do? Or the rumour of intel hitting a wall - if that`s true - is due to the fact that the architecture intel is using is a heavily modified version of P6 that was released in 1996?
If intel truly wont have a new architecture for two more generations (and will fight arm for efficiency crown), can amd surpass intel in performance with zen iterations?
There are always bottlenecks and limitations. Buffer sizes, internal bandwidth, instruction latencies, better utilization of all execution resources (I suspect this is a big one for Zen+), and, of course, frequency all play a role in performance - along with many other factors, as always. Zen+ will probably include changes specifically designed to allow one thread to better utilize all execution units. It is possible that Zen+ may be able to summarily execute certain instructions in the pipeline, bypass more stages in more scenarios, or feature a more refined FastPath implementation that simply better represents modern software.
As for hitting a performance wall, I don't see a limit across the board, but some programs' main performance-determining algorithms just aren't complex enough to be improved much beyond a certain point. However, in order for IPC to continue to scale well, we will see cores needing to grow incredibly more massive for each gain we get. We are facing a point of diminishing returns, but we could always start with brute-force and begin fetching and decoding twice as many instructions with a 50% wider core. Even with that, not all programs will be sped up much, in fact the average program will only see a 15% or so performance increase in that scenario - however, some programs could benefit immensely, and SMT could begin to scale much more. Not much return for the investment.
As for catching Intel, the gap will remain closer. I doubt AMD plans on taking on any more risky design plans and will probably try to play it safe, even if that means playing second fiddle for a few generations. That said, Intel may well misstep, or AMD may achieve parity. With Intel's FPUs being so massive, each Intel core costs more to produce than each AMD core, and I don't expect AMD to bother with native AVX512 at all for a few generations, at least. If they do, it may only be for server chips - which is assuming they are in a much better financial situation (to support two x86 FPU designs).
As far as Haswell being encumbered by its p6 heritage: yes, undoubtedly. When you look at most of Haswell's distribution of execution capabilities, you see that Ports 0 & 1 dominate the equation.
You don't need to understand what it all means, but you can clearly see that Ports 0 & 1 have the most capabilities.
If you compare that to Zen:
You see that Zen has a much more even distribution of capabilities, which means it can begin more of a diverse instruction grouping than Haswell, which is good for saving a few cycles here or there, for extracting maximum instruction level parallelism (ILP), and even a potential advantage for SMT. Zen's FPU is an odd beast, though, that's for sure. But AMD has extensive expertise for floating point computation and was well ahead of Intel for years, so I suspect that Zen's FPU will be a nice jump, and that Zen+ may well feature more FPU improvements.