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[OC3D] AMD's Zen will have a "greater than 40%" IPC improvement over Excavator, says Lisa Su - Page 73

post #721 of 841
Alright, since AMD apparently has given zen a beastly on-die memory system, what about the memory controller? Has there been any news on that and how its expected to perform? IIRC the construction core series IMCs werent all that good, and its one of the many many reasons why they sucked.
Edited by Cyrious - 2/29/16 at 9:31pm
post #722 of 841
I just hope Zen will come out ASAP and have ITX boards.
post #723 of 841
Quote:
Originally Posted by Cyrious View Post

Alright, since AMD apparently has given zen a beastly on-die memory system, what about the memory controller? Has there been any news on that and how its expected to perform? IIRC the construction core series IMCs werent all that good, and its one of the many many reasons why they sucked.

The construction cores' memory controller actually is pretty decent, it was a real step up from the K10 controller. Good news is that AMD already has a DDR4 controller and it has been in use for some time (it is in Carrizo, for example). Sadly, we won't know how it performs with DDR4 in a desktop scenario until AM4 is released - and we still won't know if that is the same controller AMD used with Zen.

Here's Bulldozer's memory controller beating Sandy Bridge:

http://www.ilsistemista.net/index.php/hardware-analysis/24-bulldozer-vs-sandy-bridge-vs-k10-comparison-whats-wrong-with-amd-bulldozer.html?start=3
post #724 of 841
Quote:
Originally Posted by looncraz View Post

The construction cores' memory controller actually is pretty decent, it was a real step up from the K10 controller. Good news is that AMD already has a DDR4 controller and it has been in use for some time (it is in Carrizo, for example). Sadly, we won't know how it performs with DDR4 in a desktop scenario until AM4 is released - and we still won't know if that is the same controller AMD used with Zen.

Here's Bulldozer's memory controller beating Sandy Bridge:

http://www.ilsistemista.net/index.php/hardware-analysis/24-bulldozer-vs-sandy-bridge-vs-k10-comparison-whats-wrong-with-amd-bulldozer.html?start=3
It had the bandwidth, yes, but the latency wasnt as good (according to the Extremetech article). Hmm. Perhaps with the new caching stuff the latency from main memory can be better handled, especially since DDR4 is higher latency vs DDR3 at the same clock.
post #725 of 841
Quote:
Originally Posted by Cyrious View Post

It had the bandwidth, yes, but the latency wasnt as good (according to the Extremetech article). Hmm. Perhaps with the new caching stuff the latency from main memory can be better handled, especially since DDR4 is higher latency vs DDR3 at the same clock.
http://www.extremetech.com/computing/177099-secrets-of-steamroller-digging-deep-into-amds-next-gen-core
post #726 of 841
post #727 of 841
So... if I'm reading these right, AMD's DDR3 controller can throw punches and sometimes win against the intel IMC? Huh, I thought AMD's was weaker. Well, guess I was wrong.
post #728 of 841
Do you see already points of possible improvements of zen? Bottlenecks that zen+ would fix?

Do you think that Amd with zen will soon hit a performance wall just like intel is said to do? Or the rumour of intel hitting a wall - if that`s true - is due to the fact that the architecture intel is using is a heavily modified version of P6 that was released in 1996?

If intel truly wont have a new architecture for two more generations (and will fight arm for efficiency crown), can amd surpass intel in performance with zen iterations?
post #729 of 841
Current performance issues are more related to how chips are made rather than the design behind them.

Clock speeds have flatlined in the consumer space.
Per core performance is slowing to a halt for general purpose code.
The only metric going up with time is the number of available cores, and current software design paradigms dont scale well with more logical or physical cores.
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post #730 of 841
Quote:
Originally Posted by Petykemano View Post

Do you see already points of possible improvements of zen? Bottlenecks that zen+ would fix?

Do you think that Amd with zen will soon hit a performance wall just like intel is said to do? Or the rumour of intel hitting a wall - if that`s true - is due to the fact that the architecture intel is using is a heavily modified version of P6 that was released in 1996?

If intel truly wont have a new architecture for two more generations (and will fight arm for efficiency crown), can amd surpass intel in performance with zen iterations?

There are always bottlenecks and limitations. Buffer sizes, internal bandwidth, instruction latencies, better utilization of all execution resources (I suspect this is a big one for Zen+), and, of course, frequency all play a role in performance - along with many other factors, as always. Zen+ will probably include changes specifically designed to allow one thread to better utilize all execution units. It is possible that Zen+ may be able to summarily execute certain instructions in the pipeline, bypass more stages in more scenarios, or feature a more refined FastPath implementation that simply better represents modern software.

As for hitting a performance wall, I don't see a limit across the board, but some programs' main performance-determining algorithms just aren't complex enough to be improved much beyond a certain point. However, in order for IPC to continue to scale well, we will see cores needing to grow incredibly more massive for each gain we get. We are facing a point of diminishing returns, but we could always start with brute-force and begin fetching and decoding twice as many instructions with a 50% wider core. Even with that, not all programs will be sped up much, in fact the average program will only see a 15% or so performance increase in that scenario - however, some programs could benefit immensely, and SMT could begin to scale much more. Not much return for the investment.

As for catching Intel, the gap will remain closer. I doubt AMD plans on taking on any more risky design plans and will probably try to play it safe, even if that means playing second fiddle for a few generations. That said, Intel may well misstep, or AMD may achieve parity. With Intel's FPUs being so massive, each Intel core costs more to produce than each AMD core, and I don't expect AMD to bother with native AVX512 at all for a few generations, at least. If they do, it may only be for server chips - which is assuming they are in a much better financial situation (to support two x86 FPU designs).

As far as Haswell being encumbered by its p6 heritage: yes, undoubtedly. When you look at most of Haswell's distribution of execution capabilities, you see that Ports 0 & 1 dominate the equation.

http://looncraz.net/HswAssignments.htm

You don't need to understand what it all means, but you can clearly see that Ports 0 & 1 have the most capabilities.

If you compare that to Zen:

http://looncraz.net/ZenAssignments.html

You see that Zen has a much more even distribution of capabilities, which means it can begin more of a diverse instruction grouping than Haswell, which is good for saving a few cycles here or there, for extracting maximum instruction level parallelism (ILP), and even a potential advantage for SMT. Zen's FPU is an odd beast, though, that's for sure. But AMD has extensive expertise for floating point computation and was well ahead of Intel for years, so I suspect that Zen's FPU will be a nice jump, and that Zen+ may well feature more FPU improvements.
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