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[OC3D] AMD's Zen will have a "greater than 40%" IPC improvement over Excavator, says Lisa Su - Page 74

post #731 of 841
I think AMD is still working on the FM2+ APU, but I don't know how this relates.

http://www.anandtech.com/show/10103/amd-launches-the-a107890k-and-athlon-x4-880k
post #732 of 841
There's a major advantage to hindsight when designing a new CPU architecture from scratch. Especially when your sole goal is to take what already exists and improve upon it.
post #733 of 841
Quote:
Originally Posted by warpuck View Post

I think AMD is still working on the FM2+ APU, but I don't know how this relates.

http://www.anandtech.com/show/10103/amd-launches-the-a107890k-and-athlon-x4-880k

Its more like the end ... well I wouldnt mind ZEN 28nm quad core with 8 threads for FM2+, if price would be low = 200% not happening
post #734 of 841
Quote:
Originally Posted by Cyrious View Post

So... if I'm reading these right, AMD's DDR3 controller can throw punches and sometimes win against the intel IMC? Huh, I thought AMD's was weaker. Well, guess I was wrong.
Maybe with the right memory the construction core memory controller can put down decent numbers. My experience says otherwise. My i7-2630qm laptop with 1333MHz DDR3 in dual channel puts down better bandwidth than my FX-6300 desktop with 1600 MHz dual channel DDR3 in every single benchmark. The desktop is running XMP with tighter timings too.
post #735 of 841
Quote:
Originally Posted by AmericanLoco View Post

Quote:
Originally Posted by Cyrious View Post

So... if I'm reading these right, AMD's DDR3 controller can throw punches and sometimes win against the intel IMC? Huh, I thought AMD's was weaker. Well, guess I was wrong.
Maybe with the right memory the construction core memory controller can put down decent numbers. My experience says otherwise. My i7-2630qm laptop with 1333MHz DDR3 in dual channel puts down better bandwidth than my FX-6300 desktop with 1600 MHz dual channel DDR3 in every single benchmark. The desktop is running XMP with tighter timings too.

Honestly.. the constructions cores shine 1866 and 2133.. 1600 is a bottleneck for them.
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post #736 of 841
Quote:
Originally Posted by looncraz View Post

That WOULD explain it. I have no idea how many dead Seagate drives I have laying around right now from other peoples' computers. I noticed Toshiba was very underrepresented and started using them when I can - so far no failures whistle.gif

I have 2 Seagate drives about 10yrs old that have out lasted around 14 WD drives tongue.gif Seagate has served me well personally but everyone has different experiences
Edited by Echoa - 3/1/16 at 2:07pm
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post #737 of 841
Quote:
Originally Posted by F3ERS 2 ASH3S View Post

Honestly.. the constructions cores shine 1866 and 2133.. 1600 is a bottleneck for them.
Still doesn't excuse the fact the SB memory controller gets more bandwidth out of slower RAM...
post #738 of 841
Quote:
Originally Posted by AmericanLoco View Post

Quote:
Originally Posted by F3ERS 2 ASH3S View Post

Honestly.. the constructions cores shine 1866 and 2133.. 1600 is a bottleneck for them.
Still doesn't excuse the fact the SB memory controller gets more bandwidth out of slower RAM...

Thats due to the high latency that the AMD dies have had since like a long time.. if you are not familiar please go back and check circa 2010... they just have not had quick caching internally on die and that is the big difference.

That is why it was such a HUGE deal that ZEN have updated and faster caching systems in the chip is very well pointed out by your comment.
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post #739 of 841
@looncraz

In that last patch note reconstruction, there was a comment about the cores having shared back ends. What precisely was meant by that? My first thought was that it's something to enable two cores to work on a single thread. It would make sense if Zen was approached by AMD as something to seriously rectify the faults of the Construction series, but I'm not sure if my brain is working properly.

Also, in the context of K9/Greyhound, how fast do you think AMD will be inclined to ramp HT beyond two threads per die? The temptation has to be there to go big socket (like G34), take the die space penalties, and just go for it.
post #740 of 841
Quote:
Originally Posted by Fyrwulf View Post

@looncraz

In that last patch note reconstruction, there was a comment about the cores having shared back ends. What precisely was meant by that? My first thought was that it's something to enable two cores to work on a single thread. It would make sense if Zen was approached by AMD as something to seriously rectify the faults of the Construction series, but I'm not sure if my brain is working properly.

Also, in the context of K9/Greyhound, how fast do you think AMD will be inclined to ramp HT beyond two threads per die? The temptation has to be there to go big socket (like G34), take the die space penalties, and just go for it.

I do know that the l3 cache is shared.. so there is that..

As far as the Die space hit, I don't think AMD would want to go that route this iteration as they are needing to reclaim the market share and bring in better profits.
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