Originally Posted by Noufel
and mister can you provide us a proof that intel isn't going HEDT skylake E with this socket in your all mighty google research knowledge
Yeah. I can.
Knight's Landing has room for 16GB of on-package cache memory:
The Broadwell-EP architecture, at least from all of the block diagrams that I've seen, doesn't have the ability to host on-package HMC (Micron's version of Samsung's HBM). Which accounts for the sheer size of the Knight's Landing CPU. So one could reasonably infer (since block diagrams for Skylake-EP haven't been released), that it will also not have the ability to host on-package HMC. And to be quite honest, I can't think of a single reason for a consumer CPU to need on package HMC. Especially if I'm understanding this correctly, Knight's Landing uses that for quick error detection and correction (because I'm 99.99999999999999999% sure they aren't using optical links to the HMC packages, so they don't need Electronic Dispersion Compensation), and consumer CPUs just don't need that.