We thoroughly tested the VDDCI of Tonga over on the Tonga Thread. By stock was 1175mv, only on Tonga would there need to be an offset so as the core clock rose so did the offset to maintain it's static 1175mv value. Which is ideal.
If you wanted to change the VDDCI, it can benefit the biggest big end of clocks. For instance 24/7 stable 1563Mhz operation.
Though there is no VDDCI Offset location in ATOM BIOS Reader for Polaris for the 65288, 65287, 65286 and so on. You want to leave idle 300Mhz at 900Mv no less or more.
So if we can actually find the exact location of the 65288 Hex Offset in the BIOS, then we could alter the VDDCI Offset to core voltage.
This won't help when not pushing super high core clocks. Though if going for huge big end clocks like 2Ghz on Polaris. The VDDCI may need to be set to 1000mv Static, rather than 900mv.
The VDDCI is the Integrated memory controller voltage. The 1000mv beside the 2000Mhz memory clock in Polaris BIOS editor is the module voltage regulator voltage at the back of the card near the 6-pin. Usually 2 VRM side by side. Unless I'm Way Off, an AMD Engineer would have to explain hahaha
If someone can set me straight please find an AMD Whitepaper going over AMD GPU VDDCI and what VDDCI means exactly and where it's coming from. We know it's voltage for memory, but could be helpful to know the particulars.
Tonga example is the same as Polaris. As the core voltage goes down it's VDDCI offset value increases. On polaris it uses very high Offset because of ultra low power consumption.
65288 : VDDCI : 1175mv : 1225mv : Offset is -50 or actually -51 in hex for CD FF
65287 : Etc
Polaris is like this...
65288 : VDDCI : 900mv : 1250mv : Offset is -350 or actually -351 in hex for FE A1 On progammer windows calc : so you have to flip it as it appears flipped in hex for value : A1 FE for 65288.Edited by chris89 - 4/2/17 at 3:50pm