Overclock.net › Forums › Graphics Cards › AMD/ATI › Polaris Bios Editing ( RX5xx / RX4xx )
New Posts  All Forums:Forum Nav:

Polaris Bios Editing ( RX5xx / RX4xx ) - Page 262

post #2611 of 3387
Just got yesterday the strix rx 480 oc for a fair price. Anyone tried strix rx 580 bios on these and is there any benefits?
post #2612 of 3387
Quote:
Originally Posted by generaleramon View Post

Reboot until advanced boot option appear, than boot in safe mode, unistall+remove driver from device manager and then reflash.

I hate to post things not tested. Sorry...
Tried, it doesn't work. Only 1+8 pin CMOS helped.
Good expirience for me)
post #2613 of 3387
I recompiled OhGodADecode for windows (32 bit so everyone is happy), all credits goes too @OhGodAGirl.

ohgodadecode.zip 103k .zip file

Later I'll create a tool to reverse the process if possible (from decoded timings to strap).
post #2614 of 3387
@generaleramon

I fixed your Uber Mix Timings from the OP.

TRCDR & TRCDRA should always be equal.

Uber mix original:
Original Uber Mix (Click to show)
Code:
--> HEX strap: 777000000000000022CC1C00AD615B41C0570E152DCB7409006007000B031420FA8900A00300000010123A46DB354019

--> MC_SEQ_WR_CTL_D0
    DAT_DLY = 7,   DQS_DLY = 7,  DQS_XTR = 0,  DAT_2Y_DLY = 0,  ADR_2Y_DLY = 0,    CMD_2Y_DLY = 0,  OEN_DLY = 7,  OEN_EXT = 0

--> MC_SEQ_WR_CTL_D1
    DAT_DLY = 0,   DQS_DLY = 0,  DQS_XTR = 0,  DAT_2Y_DLY = 0,  ADR_2Y_DLY = 0,    CMD_2Y_DLY = 0,  OEN_DLY = 0,  OEN_EXT = 0

--> MC_SEQ_PMG_TIMING
    TCKSRE = 2,  TCKSRX = 2,  TCKE_PULSE = 12,  TCKE = 12,  SEQ_IDLE = 7

--> MC_SEQ_RAS_TIMING
    TRCDW = 13,  TRCDWA = 13,  TRCDR = 24,  TRCDRA = 22,  TRRD = 5,  TRC = 65

--> MC_SEQ_CAS_TIMING
    TNOPW = 0,  TNOPR = 0,  TR2W = 28,  TCCLD = 3,  TR2R = 5,  TW2R = 14,  TCL = 21

--> MC_SEQ_MISC_TIMING
    TRP_WRA = 45,  TRP_RDA = 11,  TRP = 9,  TRFC = 151

--> MC_SEQ_MISC_TIMING2
    PA2RDATA = 0,  PA2WDATA = 0,  FAW = 0,  TREDC = 3,  TWEDC = 7,  T32AW = 0,  TWDATATR = 0

--> MC_SEQ_MISC1
 -- MR0
    WL = 3,  CL = 22,  TM = 0,  WR = 23,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 0
 -- MR1
    DS = 0,  DT = 1,  ADR = 1,  CAL = 0,  PLL = 0,  RDBI = 0,  WDBI = 0,  ABI = 0,
    RES = 0,  BA0 = 0,  BA1 = 1,  BA2 = 0,  BA3 = 0

--> MC_SEQ_MISC3
 -- MR4
    EDCHP = 10,  CRC WL = 7,  CRC RL = 3,  RD CRC = 0,  WR CRC = 0,  EDCHPi = 1,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 1
 -- MR5
    LP1 = 0,  LP2 = 0,  LP3 = 0,  PLL/DLL BW = 0,  RAS = 0,  BA0 = 0,  BA1 = 1,  BA2 = 0,  BA3 = 1


--> MC_SEQ_MISC8
 -- MR8
    CLEHF = 1,  WREHF = 1,  RFU = 0,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 0
 -- MR7
    PLL Stby = 0,  PLL Fclk = 0,  PLL DelC = 0,  LF Mode = 0,  Auto Sync = 0,  DQ PreA = 0, Temp Sensor = 0, HVFRED = 0,
    VDD Range = 0,  RFU = 0,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 0


--> MC_ARB_DRAM_TIMING
    ACTRD = 16,  ACTWR = 18,  RASMACTRD = 58,  RASMACTWR = 70

--> MC_ARB_DRAM_TIMING2
    RAS2RAS = 219,  RP = 53,  WRPLUSRP = 64,  BUS_TURN = 25

MC_SEQ_RAS_TIMING _ TRCDR = 22
Fixed Uber Mix (Click to show)
Code:
--> HEX strap: 777000000000000022CC1C00AD595B41C0570E152DCB7409006007000B031420FA8900A00300000010123A46DB354019

--> MC_SEQ_WR_CTL_D0
    DAT_DLY = 7,   DQS_DLY = 7,  DQS_XTR = 0,  DAT_2Y_DLY = 0,  ADR_2Y_DLY = 0,    CMD_2Y_DLY = 0,  OEN_DLY = 7,  OEN_EXT = 0

--> MC_SEQ_WR_CTL_D1
    DAT_DLY = 0,   DQS_DLY = 0,  DQS_XTR = 0,  DAT_2Y_DLY = 0,  ADR_2Y_DLY = 0,    CMD_2Y_DLY = 0,  OEN_DLY = 0,  OEN_EXT = 0

--> MC_SEQ_PMG_TIMING
    TCKSRE = 2,  TCKSRX = 2,  TCKE_PULSE = 12,  TCKE = 12,  SEQ_IDLE = 7

--> MC_SEQ_RAS_TIMING
    TRCDW = 13,  TRCDWA = 13,  TRCDR = 22,  TRCDRA = 22,  TRRD = 5,  TRC = 65

--> MC_SEQ_CAS_TIMING
    TNOPW = 0,  TNOPR = 0,  TR2W = 28,  TCCLD = 3,  TR2R = 5,  TW2R = 14,  TCL = 21

--> MC_SEQ_MISC_TIMING
    TRP_WRA = 45,  TRP_RDA = 11,  TRP = 9,  TRFC = 151

--> MC_SEQ_MISC_TIMING2
    PA2RDATA = 0,  PA2WDATA = 0,  FAW = 0,  TREDC = 3,  TWEDC = 7,  T32AW = 0,  TWDATATR = 0

--> MC_SEQ_MISC1
 -- MR0
    WL = 3,  CL = 22,  TM = 0,  WR = 23,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 0
 -- MR1
    DS = 0,  DT = 1,  ADR = 1,  CAL = 0,  PLL = 0,  RDBI = 0,  WDBI = 0,  ABI = 0,
    RES = 0,  BA0 = 0,  BA1 = 1,  BA2 = 0,  BA3 = 0

--> MC_SEQ_MISC3
 -- MR4
    EDCHP = 10,  CRC WL = 7,  CRC RL = 3,  RD CRC = 0,  WR CRC = 0,  EDCHPi = 1,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 1
 -- MR5
    LP1 = 0,  LP2 = 0,  LP3 = 0,  PLL/DLL BW = 0,  RAS = 0,  BA0 = 0,  BA1 = 1,  BA2 = 0,  BA3 = 1


--> MC_SEQ_MISC8
 -- MR8
    CLEHF = 1,  WREHF = 1,  RFU = 0,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 0
 -- MR7
    PLL Stby = 0,  PLL Fclk = 0,  PLL DelC = 0,  LF Mode = 0,  Auto Sync = 0,  DQ PreA = 0, Temp Sensor = 0, HVFRED = 0,
    VDD Range = 0,  RFU = 0,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 0


--> MC_ARB_DRAM_TIMING
    ACTRD = 16,  ACTWR = 18,  RASMACTRD = 58,  RASMACTWR = 70

--> MC_ARB_DRAM_TIMING2
    RAS2RAS = 219,  RP = 53,  WRPLUSRP = 64,  BUS_TURN = 25


While i was at it, fixed the light one as well smile.gif
Uber Mix Light Fix! (Click to show)
Code:
555000000000000022CC1C00AD595B41C0570E15B00B450A0068C7000B031420FA8900A0030000001B11333DC0303A17


Greetings!
Edited by Eliovp - 4/26/17 at 1:45am
post #2615 of 3387
might be the stupid question of the day. But what exactly is the benefit of flashing to the 580 bios?
AMDreams
(13 items)
 
  
CPUMotherboardGraphicsRAM
AMD Ryzen 7 1700X Asus Prime X370 Pro MSI Radeon RX 480 DX 12 GAMING X 8G Corsair Vengenance 16Gb DDR4 2666 
CoolingOSMonitorKeyboard
Corsair H110I Windows 10 Professional 64Bit Lenovo 23" LED IPS Redragon Indrah 555 RGB 
PowerCaseMouseMouse Pad
Corsair CX750M Phanteks Enthoo Pro M Mionix Naos 7000 Corsair 300m 
Audio
Logitech G430 
  hide details  
Reply
AMDreams
(13 items)
 
  
CPUMotherboardGraphicsRAM
AMD Ryzen 7 1700X Asus Prime X370 Pro MSI Radeon RX 480 DX 12 GAMING X 8G Corsair Vengenance 16Gb DDR4 2666 
CoolingOSMonitorKeyboard
Corsair H110I Windows 10 Professional 64Bit Lenovo 23" LED IPS Redragon Indrah 555 RGB 
PowerCaseMouseMouse Pad
Corsair CX750M Phanteks Enthoo Pro M Mionix Naos 7000 Corsair 300m 
Audio
Logitech G430 
  hide details  
Reply
post #2616 of 3387
Any chances someone already got their xfx rx 580 gtr-s yet and got a dump of it's bios? biggrin.gif
PepoThink (AMD)
(8 items)
 
PepoThink (Intel)
(10 items)
 
le rig
(13 items)
 
CPUMotherboardGraphicsRAM
Amd Ryzen 7 1700 ASUS Prime x370-pro XFX RX 480 GTR Black Edition Team Elite Plus DDR4 2400 8GB 
CoolingOSPowerCase
Corsair Hydro Series h110i GTX Windows 10 Enterprise N LTSB 2016 PC Power and Cooling S61EPS 610W NZXT s340 White glossy 
CPUMotherboardGraphicsRAM
7600k z270g xfx rx 480 gtr black edition team elite plus 8gb 2400 
Hard DriveCoolingOSCase
Some western digital 500GB drive h110i gtx Windows 10 Enterprise N LTSB 2016 s340 white 
OtherOther
nf-a14 IndustrialPPC 3000 nf-a14 IndustrialPPC 3000 
CPUMotherboardGraphicsHard Drive
AMD FX-8350 MSI 990fxa gaming Evga 970 ssc acx 2.0 Samsung 850 EVO 250gb 
CoolingOSCase
NH-D14 Windows 8.1 64bit Corsair 300r 
  hide details  
Reply
PepoThink (AMD)
(8 items)
 
PepoThink (Intel)
(10 items)
 
le rig
(13 items)
 
CPUMotherboardGraphicsRAM
Amd Ryzen 7 1700 ASUS Prime x370-pro XFX RX 480 GTR Black Edition Team Elite Plus DDR4 2400 8GB 
CoolingOSPowerCase
Corsair Hydro Series h110i GTX Windows 10 Enterprise N LTSB 2016 PC Power and Cooling S61EPS 610W NZXT s340 White glossy 
CPUMotherboardGraphicsRAM
7600k z270g xfx rx 480 gtr black edition team elite plus 8gb 2400 
Hard DriveCoolingOSCase
Some western digital 500GB drive h110i gtx Windows 10 Enterprise N LTSB 2016 s340 white 
OtherOther
nf-a14 IndustrialPPC 3000 nf-a14 IndustrialPPC 3000 
CPUMotherboardGraphicsHard Drive
AMD FX-8350 MSI 990fxa gaming Evga 970 ssc acx 2.0 Samsung 850 EVO 250gb 
CoolingOSCase
NH-D14 Windows 8.1 64bit Corsair 300r 
  hide details  
Reply
post #2617 of 3387
Quote:
Originally Posted by Eliovp View Post

@generaleramon

I fixed your Uber Mix Timings from the OP.

TRCDR & TRCDRA should always be equal.

Uber mix original:
Original Uber Mix (Click to show)
Code:
--> HEX strap: 777000000000000022CC1C00AD615B41C0570E152DCB7409006007000B031420FA8900A00300000010123A46DB354019

--> MC_SEQ_WR_CTL_D0
    DAT_DLY = 7,   DQS_DLY = 7,  DQS_XTR = 0,  DAT_2Y_DLY = 0,  ADR_2Y_DLY = 0,    CMD_2Y_DLY = 0,  OEN_DLY = 7,  OEN_EXT = 0

--> MC_SEQ_WR_CTL_D1
    DAT_DLY = 0,   DQS_DLY = 0,  DQS_XTR = 0,  DAT_2Y_DLY = 0,  ADR_2Y_DLY = 0,    CMD_2Y_DLY = 0,  OEN_DLY = 0,  OEN_EXT = 0

--> MC_SEQ_PMG_TIMING
    TCKSRE = 2,  TCKSRX = 2,  TCKE_PULSE = 12,  TCKE = 12,  SEQ_IDLE = 7

--> MC_SEQ_RAS_TIMING
    TRCDW = 13,  TRCDWA = 13,  TRCDR = 24,  TRCDRA = 22,  TRRD = 5,  TRC = 65

--> MC_SEQ_CAS_TIMING
    TNOPW = 0,  TNOPR = 0,  TR2W = 28,  TCCLD = 3,  TR2R = 5,  TW2R = 14,  TCL = 21

--> MC_SEQ_MISC_TIMING
    TRP_WRA = 45,  TRP_RDA = 11,  TRP = 9,  TRFC = 151

--> MC_SEQ_MISC_TIMING2
    PA2RDATA = 0,  PA2WDATA = 0,  FAW = 0,  TREDC = 3,  TWEDC = 7,  T32AW = 0,  TWDATATR = 0

--> MC_SEQ_MISC1
 -- MR0
    WL = 3,  CL = 22,  TM = 0,  WR = 23,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 0
 -- MR1
    DS = 0,  DT = 1,  ADR = 1,  CAL = 0,  PLL = 0,  RDBI = 0,  WDBI = 0,  ABI = 0,
    RES = 0,  BA0 = 0,  BA1 = 1,  BA2 = 0,  BA3 = 0

--> MC_SEQ_MISC3
 -- MR4
    EDCHP = 10,  CRC WL = 7,  CRC RL = 3,  RD CRC = 0,  WR CRC = 0,  EDCHPi = 1,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 1
 -- MR5
    LP1 = 0,  LP2 = 0,  LP3 = 0,  PLL/DLL BW = 0,  RAS = 0,  BA0 = 0,  BA1 = 1,  BA2 = 0,  BA3 = 1


--> MC_SEQ_MISC8
 -- MR8
    CLEHF = 1,  WREHF = 1,  RFU = 0,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 0
 -- MR7
    PLL Stby = 0,  PLL Fclk = 0,  PLL DelC = 0,  LF Mode = 0,  Auto Sync = 0,  DQ PreA = 0, Temp Sensor = 0, HVFRED = 0,
    VDD Range = 0,  RFU = 0,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 0


--> MC_ARB_DRAM_TIMING
    ACTRD = 16,  ACTWR = 18,  RASMACTRD = 58,  RASMACTWR = 70

--> MC_ARB_DRAM_TIMING2
    RAS2RAS = 219,  RP = 53,  WRPLUSRP = 64,  BUS_TURN = 25

MC_SEQ_RAS_TIMING _ TRCDR = 22
Fixed Uber Mix (Click to show)
Code:
--> HEX strap: 777000000000000022CC1C00AD595B41C0570E152DCB7409006007000B031420FA8900A00300000010123A46DB354019

--> MC_SEQ_WR_CTL_D0
    DAT_DLY = 7,   DQS_DLY = 7,  DQS_XTR = 0,  DAT_2Y_DLY = 0,  ADR_2Y_DLY = 0,    CMD_2Y_DLY = 0,  OEN_DLY = 7,  OEN_EXT = 0

--> MC_SEQ_WR_CTL_D1
    DAT_DLY = 0,   DQS_DLY = 0,  DQS_XTR = 0,  DAT_2Y_DLY = 0,  ADR_2Y_DLY = 0,    CMD_2Y_DLY = 0,  OEN_DLY = 0,  OEN_EXT = 0

--> MC_SEQ_PMG_TIMING
    TCKSRE = 2,  TCKSRX = 2,  TCKE_PULSE = 12,  TCKE = 12,  SEQ_IDLE = 7

--> MC_SEQ_RAS_TIMING
    TRCDW = 13,  TRCDWA = 13,  TRCDR = 22,  TRCDRA = 22,  TRRD = 5,  TRC = 65

--> MC_SEQ_CAS_TIMING
    TNOPW = 0,  TNOPR = 0,  TR2W = 28,  TCCLD = 3,  TR2R = 5,  TW2R = 14,  TCL = 21

--> MC_SEQ_MISC_TIMING
    TRP_WRA = 45,  TRP_RDA = 11,  TRP = 9,  TRFC = 151

--> MC_SEQ_MISC_TIMING2
    PA2RDATA = 0,  PA2WDATA = 0,  FAW = 0,  TREDC = 3,  TWEDC = 7,  T32AW = 0,  TWDATATR = 0

--> MC_SEQ_MISC1
 -- MR0
    WL = 3,  CL = 22,  TM = 0,  WR = 23,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 0
 -- MR1
    DS = 0,  DT = 1,  ADR = 1,  CAL = 0,  PLL = 0,  RDBI = 0,  WDBI = 0,  ABI = 0,
    RES = 0,  BA0 = 0,  BA1 = 1,  BA2 = 0,  BA3 = 0

--> MC_SEQ_MISC3
 -- MR4
    EDCHP = 10,  CRC WL = 7,  CRC RL = 3,  RD CRC = 0,  WR CRC = 0,  EDCHPi = 1,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 1
 -- MR5
    LP1 = 0,  LP2 = 0,  LP3 = 0,  PLL/DLL BW = 0,  RAS = 0,  BA0 = 0,  BA1 = 1,  BA2 = 0,  BA3 = 1


--> MC_SEQ_MISC8
 -- MR8
    CLEHF = 1,  WREHF = 1,  RFU = 0,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 0
 -- MR7
    PLL Stby = 0,  PLL Fclk = 0,  PLL DelC = 0,  LF Mode = 0,  Auto Sync = 0,  DQ PreA = 0, Temp Sensor = 0, HVFRED = 0,
    VDD Range = 0,  RFU = 0,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 0


--> MC_ARB_DRAM_TIMING
    ACTRD = 16,  ACTWR = 18,  RASMACTRD = 58,  RASMACTWR = 70

--> MC_ARB_DRAM_TIMING2
    RAS2RAS = 219,  RP = 53,  WRPLUSRP = 64,  BUS_TURN = 25


While i was at it, fixed the light one as well smile.gif
Uber Mix Light Fix! (Click to show)
Code:
555000000000000022CC1C00AD595B41C0570E15B00B450A0068C7000B031420FA8900A0030000001B11333DC0303A17


Greetings!

Where did you get all the infos about timings? I mean dependencies/relations between timings... As exemple, like you said: " TRCDR & TRCDRA should always be equal.", Nice to know! But how did you know that? Is there some king of documentation somewhere? Or I simply follow the same rules/tweals that I can find for common/usual/non-graphics ddr memory timings
post #2618 of 3387
Quote:
Originally Posted by Vento041 View Post

Where did you get all the infos about timings? I mean dependencies/relations between timings... As exemple, like you said: " TRCDR & TRCDRA should always be equal.", Nice to know! But how did you know that? Is there some king of documentation somewhere? Or I simply follow the same rules/tweals that I can find for common/usual/non-graphics ddr memory timings

A lot of reading and experimenting helps smile.gif

Common usual non graphics ddr memory knowledge helps a lot! So yes, you're right there.

Also the JEDEC-gddr5 standards, helps as well.

Greetings!
post #2619 of 3387
Quote:
Originally Posted by Vento041 View Post

I recompiled OhGodADecode for windows (32 bit so everyone is happy), all credits goes too @OhGodAGirl.

ohgodadecode.zip 103k .zip file

Later I'll create a tool to reverse the process if possible (from decoded timings to strap).

Nice, but it doesn't work for me. When I open it, a command console prompts and immediately it closes. Tried administrator mode and compatibility and nothing happens. W10 btw.
post #2620 of 3387
Quote:
Originally Posted by Ansau View Post

Quote:
Originally Posted by Vento041 View Post

I recompiled OhGodADecode for windows (32 bit so everyone is happy), all credits goes too @OhGodAGirl.

ohgodadecode.zip 103k .zip file

Later I'll create a tool to reverse the process if possible (from decoded timings to strap).

Nice, but it doesn't work for me. When I open it, a command console prompts and immediately it closes. Tried administrator mode and compatibility and nothing happens. W10 btw.

Navigate to folder in explorer and Shift+Right click and "Open command window here". Run "ohgodadecode.exe" "HEX VALUE" to get the decode output.

example in cmd:

INPUT:
ohgodadecode.exe 777000000000000022CC1C00AD595B41C0570E152DCB7409006007000B031420FA8900A00300000010123A46DB354019

OUTPUT:
TRCDW=13 TRCDWA=13 TRCDR=22 TRCDRA=22 TRRD=5 TRC=65 Pad0=0

TNOPW=0 TNOPR=0 TR2W=28 TCCDL=3 TR2R=5 TW2R=14 Pad0=0 TCL=21 Pad1=0

TRP_WRA=45 TRP_RDA=22 TRP=19 TRFC=151 Pad0=0

PA2RDATA=0 Pad0=0 PA2WDATA=0 Pad1=0 TFAW=0 TCRCRL=3 TCRCWL=7 TFAW32=0

MC_SEQ_MISC1: 0x2014030B
MC_SEQ_MISC3: 0xA00089FA
MC_SEQ_MISC8: 0x00000003

ACTRD=16 ACTWR=18 RASMACTRD=58 RASMACTWR=70

RAS2RAS=219 RP=53 WRPLUSRP=64 BUS_TURN=25
New Posts  All Forums:Forum Nav:
  Return Home
  Back to Forum: AMD/ATI
Overclock.net › Forums › Graphics Cards › AMD/ATI › Polaris Bios Editing ( RX5xx / RX4xx )