Overclock.net › Forums › Graphics Cards › AMD/ATI › Polaris Bios Editing ( RX5xx / RX4xx )
New Posts  All Forums:Forum Nav:

Polaris Bios Editing ( RX5xx / RX4xx ) - Page 54

post #531 of 3354
I re-flashed the stock bios for a 2nd time. did a 2nd ddu and a power off cold boot before loading the driver. Now my memory clocks fine again. What the heck? How could faulty memory timings be persistent through 2 bios flashes? Why did it take 3? I don't get it. I still have video memory issues with my card but they are no worse than when the card was new. So I'm back where I started and I'll probably quit while I'm ahead. Any ideas how those timings could be persistent?

Sapphire finally responded. They want me to take a picture of the back of the card. I'm on water. Should I just tell them I'm on water? Probably be the honest thing to do. Worst case I wait until the next credit card billing cycle and buy another card on the 20th right? This time xfs since they allow water blocks as long as the water block isn't what caused the issue and you can return the card to it's original.
post #532 of 3354
Got my hands on another Sapphire RX480 reference 4GB, when I plug it in and run Memoryinfo I get no Memory Name, it's blank. It says memory size is 4gb and memory density is 128MX32 however I believe that's just what the BIOS tells it.. Is there a way to check without lifting the cooler?

EDIT: Took the cooler off, the chips were 8GB density, flashed to 8GB all is good. However, I had to remove the paste on the cooler/chip and replace with what I had at hand. It idles at around 45-46C, mainboard temp at 32C and CPU socket at 36C (cores at 20C). Is this a normal idle temp?
Edited by appiah4 - 9/3/16 at 5:34pm
Atlas
(12 items)
 
  
CPUMotherboardGraphicsRAM
AMD FX 8300 ASUS M5A97 R2.0 Sapphire Radeon RX 480 8GB GSkill 2x4GB DDR1333 Value Ram 
Hard DriveHard DriveOptical DriveCooling
OCZ Agility 120G SSD WD Blue 1TB HDD ASUS 24x8x52 DVD/CD-RW Cooler Master Hyper T4 
OSMonitorPowerCase
Windows 7 64-bit Dell P2414H High Power ECO 500W Zalman Z3 Plus White 
  hide details  
Reply
Atlas
(12 items)
 
  
CPUMotherboardGraphicsRAM
AMD FX 8300 ASUS M5A97 R2.0 Sapphire Radeon RX 480 8GB GSkill 2x4GB DDR1333 Value Ram 
Hard DriveHard DriveOptical DriveCooling
OCZ Agility 120G SSD WD Blue 1TB HDD ASUS 24x8x52 DVD/CD-RW Cooler Master Hyper T4 
OSMonitorPowerCase
Windows 7 64-bit Dell P2414H High Power ECO 500W Zalman Z3 Plus White 
  hide details  
Reply
post #533 of 3354
Quote:
Originally Posted by mynm View Post

If "Memory voltage control" is a "dummy" feature on 480, and 380 have and NCP81022 that is as well an only one loop controller.
Do you think that what you and The Stilt confirmed to be VDDCI on 380 is a "dummy" feature as well?

NCP81022 is "Dual Output 4 Phase Plus 1 Phase" , ie it has one output with 4 phases and second output with 1 phase, I would assume VDDCI is on the second output (ie 1 phase). I don't think it is dummy feature on 380 a) from what The Stilt stated b) from what you see in monitoring data.

IR3567B is "Dual Output 6 Phase Plus 2 Phase" , in the context of the ref PCB RX 480 the 6 phase output is used for GPU and the second 2 phase output is unused (confirmed by The Stilt). Memory voltage control is dummy feature in WattMan on ref PCB RX 480 as VRM for memory voltage has no programmable control chip employed.

VDDCI on RX 480 seems is also "Dynamic" on Polaris, I manually marked PowerPlay table header and some other bits I was interested in, in spoiler platform caps translated near end.

Polaris partial PP marking (Click to show)
Code:
ATOM_COMMON_TABLE_HEADER sHeader;

00              UCHAR  ucTableRevision;
4D 00           USHORT usTableSize;                                             /*the size of header structure */

0A 06 00 00     ULONG   ulGoldenPPID;
3B 24 00 00     ULONG   ulGoldenRevision;
19 00           USHORT  usFormatID;

00 00           USHORT  usVoltageTime;                                   /*in microseconds */
00 80 02 01     ULONG   ulPlatformCaps;                                   /*See ATOM_Tonga_CAPS_* */

40 0D 03 00     ULONG   ulMaxODEngineClock;                        /*For Overdrive.  */
E8 6E 03 00     ULONG   ulMaxODMemoryClock;                        /*For Overdrive. */

32 00           USHORT  usPowerControlLimit;
32 00           USHORT  usUlvVoltageOffset;                               /*in mv units */

4D 00           USHORT  usStateArrayOffset;                               /*points to ATOM_Tonga_State_Array */
94 02           USHORT  usFanTableOffset;                                 /*points to ATOM_Tonga_Fan_Table */
8B 02           USHORT  usThermalControllerOffset;                 /*points to ATOM_Tonga_Thermal_Controller */
00 00           USHORT  usReserv;                       /*CustomThermalPolicy removed for Tonga. Keep this filed as reserved. */

B5 01           USHORT  usMclkDependencyTableOffset;       /*points to ATOM_Tonga_MCLK_Dependency_Table */
3B 01           USHORT  usSclkDependencyTableOffset;       /*points to ATOM_Tonga_SCLK_Dependency_Table */
77 00           USHORT  usVddcLookupTableOffset;                   /*points to ATOM_Tonga_Voltage_Lookup_Table */
F9 00           USHORT  usVddgfxLookupTableOffset;              /*points to ATOM_Tonga_Voltage_Lookup_Table */

D1 01           USHORT  usMMDependencyTableOffset;                /*points to ATOM_Tonga_MM_Dependency_Table */

F9 02           USHORT  usVCEStateTableOffset;                     /*points to ATOM_Tonga_VCE_State_Table; */

00 00           USHORT  usPPMTableOffset;                                 /*points to ATOM_Tonga_PPM_Table */
C4 02           USHORT  usPowerTuneTableOffset;                   /*points to ATOM_PowerTune_Table */

00 00           USHORT  usHardLimitTableOffset;                    /*points to ATOM_Tonga_Hard_Limit_Table */

13 03           USHORT  usPCIETableOffset;                                /*points to ATOM_Tonga_PCIE_Table */

2D 03           USHORT  usGPIOTableOffset;                                /*points to ATOM_Tonga_GPIO_Table */

000000000000000000000000        USHORT  usReserved[6];                                     /*TODO: modify reserved size to fit structure aligning */

typedef struct _ATOM_Tonga_MCLK_Dependency_Table {
00      UCHAR ucRevId;
02      UCHAR ucNumEntries;                                                                             /* Number of entries. */
        ATOM_Tonga_MCLK_Dependency_Record entries[1];                           /* Dynamically allocate entries. */
} ATOM_Tonga_MCLK_Dependency_Table;

typedef struct _ATOM_Tonga_MCLK_Dependency_Record {
00      UCHAR  ucVddcInd;       /* Vddc voltage */
52 03   USHORT usVddci;
00 00   USHORT usVddgfxOffset;  /* Offset relative to Vddc voltage */
E8 03   USHORT usMvdd;
30 75 00 00     ULONG ulMclk;
00 00   USHORT usReserved;
} ATOM_Tonga_MCLK_Dependency_Record;

        typedef struct _ATOM_Tonga_MCLK_Dependency_Record {
0F      UCHAR  ucVddcInd;       /* Vddc voltage */
B6 03   USHORT usVddci;
00 00   USHORT usVddgfxOffset;  /* Offset relative to Vddc voltage */
E8 03   USHORT usMvdd;
40 0D 03 00     ULONG ulMclk;
00 00   USHORT usReserved;
} ATOM_Tonga_MCLK_Dependency_Record;


typedef struct _ATOM_Fiji_PowerTune_Table {

04      UCHAR  ucRevId;
6E 00   USHORT usTDP;
00 00   USHORT usConfigurableTDP;
6B 00   USHORT usTDC;
6E 00   USHORT usBatteryPowerLimit;
6E 00   USHORT usSmallPowerLimit;
00 00   USHORT usLowCACLeakage;
00 00   USHORT usHighCACLeakage;
6E 00   USHORT usMaximumPowerDeliveryLimit;
5A 00   USHORT usTjMax;  /* For Fiji, this is also usTemperatureLimitEdge; */
00 00   USHORT usPowerTuneDataSetID;
00 00   USHORT usEDCLimit;
5E 00   USHORT usSoftwareShutdownTemp;
02 00   USHORT usClockStretchAmount;
69 00   USHORT usTemperatureLimitHotspot;  /*The following are added for Fiji */
50 00   USHORT usTemperatureLimitLiquid1;
50 00   USHORT usTemperatureLimitLiquid2;
73 00   USHORT usTemperatureLimitVrVddc;
73 00   USHORT usTemperatureLimitVrMvdd;
5F 00   USHORT usTemperatureLimitPlx;
00      UCHAR  ucLiquid1_I2C_address;  /*Liquid */
00      UCHAR  ucLiquid2_I2C_address;
90      UCHAR  ucLiquid_I2C_Line;
10      UCHAR  ucVr_I2C_address;        /*VR */
96      UCHAR  ucVr_I2C_Line;
00      UCHAR  ucPlx_I2C_address;  /*PLX */
90      UCHAR  ucPlx_I2C_Line;
00 00   USHORT usReserved;

Platform cap

00 80 02 01

01 02 80 00

01 00 00 00 ATOM_TONGA_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL  0x1000000     /* Enable to indicate if thermal and PCC are sharing the same GPIO */
00 02 00 00 ATOM_TONGA_PP_PLATFORM_CAP_BACO                    0x20000            /* Enable to indicate the driver supports BACO state. */
00 00 80 00 ATOM_TONGA_PP_PLATFORM_CAP_VDDCI_CONTROL           0x8000            /* This cap indicates dynamic VDDCI is required. Uncheck to disable it. */

Just like Memory VRM the VDDCI seems to not have a control chip with data interface/monitoring as last time I saw HWiNFO running on a ref PCB RX 480 it did not show a voltage like VDDCI. To me this would also mean IR3567B is not controlling VDDCI on RX 480.

ATOM_Tonga_MCLK_Dependency_Record is a weird table in that how it's labelled isn't how it's implemented for MVDD. Now E8 03 USHORT usMvdd; the E8 03 as you know is 1000mV no way would GDDR5 do the frequency it's at for that MVDD. We also saw similar thing for that table in Tonga/Fiji ROM which use the same revision of PowerPlay as Polaris.

Now definitely on Fiji HBM is controlled by IR3567B and it most definitely shows monitoring data for HBM voltage and in PowerPlay it has 1000mV as MVDD but it isn't a) that voltage it's 1300mV@stock, confirmed by DMM/SW monitoring/IR3567B registers b) isn't controlled by that table.

Fiji PP MCLK Table (Click to show)
Code:
ATOM_Tonga_MCLK_Dependency_Record

00                      UCHAR ucRevId;
01                      UCHAR ucNumEntries;     /* Number of entries. */
00                      UCHAR  ucVddcInd;       /* Vddc voltage */
E803 (1000mV)           USHORT usVddci;
0000                    USHORT usVddgfxOffset;  /* Offset relative to Vddc voltage */
E803 (1000mV)           USHORT usMvdd;
50C30000 (500MHz)       ULONG ulMclk;
0000                    USHORT usReserved;
XPS - R7 1700
(14 items)
 
XPS - i5 4690K
(12 items)
 
XPS - Q6600
(8 items)
 
CPUMotherboardGraphicsRAM
Ryzen 7 1700 Asus Crosshair VI Hero Sapphire Fury X@1145/545 G.Skill Trident Z 2x 8GB 3200MHz C14 
Hard DriveCoolingCoolingCooling
Samsung Evo 840 ThermalRight Archon IB-E X2 + 2x TY143 ThermalRight TY-143 2x front case intake Arctic Cooling F12 + 2x F9 as rear case exhaust 
OSMonitorKeyboardPower
Win 7 Pro x64 / Win 10 Pro x64 Asus MG279Q Cherry MX-Board 3.0 Cooler Master V850 
CaseMouse
SilverStone TJ06 Logitech G700S 
CPUMotherboardGraphicsRAM
i5 4690K@4.9GHz 1.255V Asus Maximus VII Ranger Sapphire Fury X@1145/545 HyperX Savage 2x8GB 2400MHz C11 
Hard DriveCoolingOSMonitor
Samsung Evo 840 TR Archon SB-E X2 Win 7 Pro x64 / Win 10 x64 Asus MG279Q 
KeyboardPowerCaseMouse
Cherry MX-Board 3.0 Cooler Master V850 SilverStone TJ06 Logitech G700S 
CPUMotherboardGraphicsRAM
Intel Q6600 G0 Asus P5K Premium Black Pearl Sapphire Toxic HD5850 Corsair Dominator 4GB 
Hard DriveCoolingOSPower
Crucial MX 100 256GB TR TRUE Rev.A Win 7 Pro x64 Cooler Master V650 
  hide details  
Reply
XPS - R7 1700
(14 items)
 
XPS - i5 4690K
(12 items)
 
XPS - Q6600
(8 items)
 
CPUMotherboardGraphicsRAM
Ryzen 7 1700 Asus Crosshair VI Hero Sapphire Fury X@1145/545 G.Skill Trident Z 2x 8GB 3200MHz C14 
Hard DriveCoolingCoolingCooling
Samsung Evo 840 ThermalRight Archon IB-E X2 + 2x TY143 ThermalRight TY-143 2x front case intake Arctic Cooling F12 + 2x F9 as rear case exhaust 
OSMonitorKeyboardPower
Win 7 Pro x64 / Win 10 Pro x64 Asus MG279Q Cherry MX-Board 3.0 Cooler Master V850 
CaseMouse
SilverStone TJ06 Logitech G700S 
CPUMotherboardGraphicsRAM
i5 4690K@4.9GHz 1.255V Asus Maximus VII Ranger Sapphire Fury X@1145/545 HyperX Savage 2x8GB 2400MHz C11 
Hard DriveCoolingOSMonitor
Samsung Evo 840 TR Archon SB-E X2 Win 7 Pro x64 / Win 10 x64 Asus MG279Q 
KeyboardPowerCaseMouse
Cherry MX-Board 3.0 Cooler Master V850 SilverStone TJ06 Logitech G700S 
CPUMotherboardGraphicsRAM
Intel Q6600 G0 Asus P5K Premium Black Pearl Sapphire Toxic HD5850 Corsair Dominator 4GB 
Hard DriveCoolingOSPower
Crucial MX 100 256GB TR TRUE Rev.A Win 7 Pro x64 Cooler Master V650 
  hide details  
Reply
post #534 of 3354
Hi everyone,

I have rx480 red devils edition from powercolour, i'm editing the unlocked rom with polaris bios editor.
i replaced the atikmdag.sys, when i reboot the pc after flash windows gives following error in device manager:

Windows has stopped this device because it has reported problems. (Code 43)

when i flash unlocked bios from Powercoolour again, it works again

any toughts??
post #535 of 3354
Quote:
Originally Posted by gupsterg View Post

Warning: Spoiler! (Click to show)
NCP81022 is "Dual Output 4 Phase Plus 1 Phase" , ie it has one output with 4 phases and second output with 1 phase, I would assume VDDCI is on the second output (ie 1 phase). I don't think it is dummy feature on 380 a) from what The Stilt stated b) from what you see in monitoring data.

IR3567B is "Dual Output 6 Phase Plus 2 Phase" , in the context of the ref PCB RX 480 the 6 phase output is used for GPU and the second 2 phase output is unused (confirmed by The Stilt). Memory voltage control is dummy feature in WattMan on ref PCB RX 480 as VRM for memory voltage has no programmable control chip employed.

VDDCI on RX 480 seems is also "Dynamic" on Polaris, I manually marked PowerPlay table header and some other bits I was interested in, in spoiler platform caps translated near end.

Polaris partial PP marking (Click to show)
Code:
ATOM_COMMON_TABLE_HEADER sHeader;

00              UCHAR  ucTableRevision;
4D 00           USHORT usTableSize;                                             /*the size of header structure */

0A 06 00 00     ULONG   ulGoldenPPID;
3B 24 00 00     ULONG   ulGoldenRevision;
19 00           USHORT  usFormatID;

00 00           USHORT  usVoltageTime;                                   /*in microseconds */
00 80 02 01     ULONG   ulPlatformCaps;                                   /*See ATOM_Tonga_CAPS_* */

40 0D 03 00     ULONG   ulMaxODEngineClock;                        /*For Overdrive.  */
E8 6E 03 00     ULONG   ulMaxODMemoryClock;                        /*For Overdrive. */

32 00           USHORT  usPowerControlLimit;
32 00           USHORT  usUlvVoltageOffset;                               /*in mv units */

4D 00           USHORT  usStateArrayOffset;                               /*points to ATOM_Tonga_State_Array */
94 02           USHORT  usFanTableOffset;                                 /*points to ATOM_Tonga_Fan_Table */
8B 02           USHORT  usThermalControllerOffset;                 /*points to ATOM_Tonga_Thermal_Controller */
00 00           USHORT  usReserv;                       /*CustomThermalPolicy removed for Tonga. Keep this filed as reserved. */

B5 01           USHORT  usMclkDependencyTableOffset;       /*points to ATOM_Tonga_MCLK_Dependency_Table */
3B 01           USHORT  usSclkDependencyTableOffset;       /*points to ATOM_Tonga_SCLK_Dependency_Table */
77 00           USHORT  usVddcLookupTableOffset;                   /*points to ATOM_Tonga_Voltage_Lookup_Table */
F9 00           USHORT  usVddgfxLookupTableOffset;              /*points to ATOM_Tonga_Voltage_Lookup_Table */

D1 01           USHORT  usMMDependencyTableOffset;                /*points to ATOM_Tonga_MM_Dependency_Table */

F9 02           USHORT  usVCEStateTableOffset;                     /*points to ATOM_Tonga_VCE_State_Table; */

00 00           USHORT  usPPMTableOffset;                                 /*points to ATOM_Tonga_PPM_Table */
C4 02           USHORT  usPowerTuneTableOffset;                   /*points to ATOM_PowerTune_Table */

00 00           USHORT  usHardLimitTableOffset;                    /*points to ATOM_Tonga_Hard_Limit_Table */

13 03           USHORT  usPCIETableOffset;                                /*points to ATOM_Tonga_PCIE_Table */

2D 03           USHORT  usGPIOTableOffset;                                /*points to ATOM_Tonga_GPIO_Table */

000000000000000000000000        USHORT  usReserved[6];                                     /*TODO: modify reserved size to fit structure aligning */

typedef struct _ATOM_Tonga_MCLK_Dependency_Table {
00      UCHAR ucRevId;
02      UCHAR ucNumEntries;                                                                             /* Number of entries. */
        ATOM_Tonga_MCLK_Dependency_Record entries[1];                           /* Dynamically allocate entries. */
} ATOM_Tonga_MCLK_Dependency_Table;

typedef struct _ATOM_Tonga_MCLK_Dependency_Record {
00      UCHAR  ucVddcInd;       /* Vddc voltage */
52 03   USHORT usVddci;
00 00   USHORT usVddgfxOffset;  /* Offset relative to Vddc voltage */
E8 03   USHORT usMvdd;
30 75 00 00     ULONG ulMclk;
00 00   USHORT usReserved;
} ATOM_Tonga_MCLK_Dependency_Record;

        typedef struct _ATOM_Tonga_MCLK_Dependency_Record {
0F      UCHAR  ucVddcInd;       /* Vddc voltage */
B6 03   USHORT usVddci;
00 00   USHORT usVddgfxOffset;  /* Offset relative to Vddc voltage */
E8 03   USHORT usMvdd;
40 0D 03 00     ULONG ulMclk;
00 00   USHORT usReserved;
} ATOM_Tonga_MCLK_Dependency_Record;


typedef struct _ATOM_Fiji_PowerTune_Table {

04      UCHAR  ucRevId;
6E 00   USHORT usTDP;
00 00   USHORT usConfigurableTDP;
6B 00   USHORT usTDC;
6E 00   USHORT usBatteryPowerLimit;
6E 00   USHORT usSmallPowerLimit;
00 00   USHORT usLowCACLeakage;
00 00   USHORT usHighCACLeakage;
6E 00   USHORT usMaximumPowerDeliveryLimit;
5A 00   USHORT usTjMax;  /* For Fiji, this is also usTemperatureLimitEdge; */
00 00   USHORT usPowerTuneDataSetID;
00 00   USHORT usEDCLimit;
5E 00   USHORT usSoftwareShutdownTemp;
02 00   USHORT usClockStretchAmount;
69 00   USHORT usTemperatureLimitHotspot;  /*The following are added for Fiji */
50 00   USHORT usTemperatureLimitLiquid1;
50 00   USHORT usTemperatureLimitLiquid2;
73 00   USHORT usTemperatureLimitVrVddc;
73 00   USHORT usTemperatureLimitVrMvdd;
5F 00   USHORT usTemperatureLimitPlx;
00      UCHAR  ucLiquid1_I2C_address;  /*Liquid */
00      UCHAR  ucLiquid2_I2C_address;
90      UCHAR  ucLiquid_I2C_Line;
10      UCHAR  ucVr_I2C_address;        /*VR */
96      UCHAR  ucVr_I2C_Line;
00      UCHAR  ucPlx_I2C_address;  /*PLX */
90      UCHAR  ucPlx_I2C_Line;
00 00   USHORT usReserved;

Platform cap

00 80 02 01

01 02 80 00

01 00 00 00 ATOM_TONGA_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL  0x1000000     /* Enable to indicate if thermal and PCC are sharing the same GPIO */
00 02 00 00 ATOM_TONGA_PP_PLATFORM_CAP_BACO                    0x20000            /* Enable to indicate the driver supports BACO state. */
00 00 80 00 ATOM_TONGA_PP_PLATFORM_CAP_VDDCI_CONTROL           0x8000            /* This cap indicates dynamic VDDCI is required. Uncheck to disable it. */

Just like Memory VRM the VDDCI seems to not have a control chip with data interface/monitoring as last time I saw HWiNFO running on a ref PCB RX 480 it did not show a voltage like VDDCI. To me this would also mean IR3567B is not controlling VDDCI on RX 480.

ATOM_Tonga_MCLK_Dependency_Record is a weird table in that how it's labelled isn't how it's implemented for MVDD. Now E8 03 USHORT usMvdd; the E8 03 as you know is 1000mV no way would GDDR5 do the frequency it's at for that MVDD. We also saw similar thing for that table in Tonga/Fiji ROM which use the same revision of PowerPlay as Polaris.

Now definitely on Fiji HBM is controlled by IR3567B and it most definitely shows monitoring data for HBM voltage and in PowerPlay it has 1000mV as MVDD but it isn't a) that voltage it's 1300mV@stock, confirmed by DMM/SW monitoring/IR3567B registers b) isn't controlled by that table.

Fiji PP MCLK Table (Click to show)
Code:
ATOM_Tonga_MCLK_Dependency_Record

00                      UCHAR ucRevId;
01                      UCHAR ucNumEntries;     /* Number of entries. */
00                      UCHAR  ucVddcInd;       /* Vddc voltage */
E803 (1000mV)           USHORT usVddci;
0000                    USHORT usVddgfxOffset;  /* Offset relative to Vddc voltage */
E803 (1000mV)           USHORT usMvdd;
50C30000 (500MHz)       ULONG ulMclk;
0000                    USHORT usReserved;

Thank you very much for the answer.

The problem, as you know, is that I can controll VDDCI (previously named MVDDC on hwinfo64), with per DPM usVddcOffset at SCLK_Dependency_Record.
Warning: Spoiler! (Click to show)
Code:
typedef struct _ATOM_Tonga_SCLK_Dependency_Record {
        UCHAR  ucVddInd;                                                                                        /* Base voltage */
        USHORT usVddcOffset;                                                                            /* Offset relative to base voltage */
        ULONG ulSclk;
        USHORT usEdcCurrent;
        UCHAR  ucReliabilityTemperature;
        UCHAR  ucCKSVOffsetandDisable;                                                    /* Bits 0~6: Voltage offset for CKS, Bit 7: Disable/enable for the SCLK level. */
} ATOM_Tonga_SCLK_Dependency_Record;

Per DPM VDCCI is the result of substracting per DPM usVddcOffset to per DPM usVdd located at usVddgfxLookupTable.

So it sounds like wattman "Memory voltage control", so perhaps is VDDCI on 480. You can't see "memory voltage" or VDDCI at hwinfo, but perhaps changing per DPM usVddcOffset, wattman per DPM "Memory voltage control" could be changed. But I see that ony the last mvddc can be changed on wattman (on one screnshot, I don't have one 480) and that usVddcOffset for the last DPM is 0, so perhaps VDDCI is limited on 480 and not on 380.
That's why I'm having problems because modding per DPM voltage is increasing VDDCI to high values. The only solution for this is moddig usVddcOffsets, or adding an voltage offset at VoltageObjectInfo table, but I don't know how to do it, I will see how to do it at hawaii mod thread, and I will ask for help there.

I'm going to try to do a guide at 285, 380(x) bios mod thread, of how to mod VDDCI, so I what to be sure that VDDCI controll isn't a "dummy" feature at 380.
post #536 of 3354
No worries on info smile.gif , sorry for delayed response just been avoiding being on OCN as my PM inbox resembles like a mini forum for AMD bios mod requests and help redface.gif .

Yes, I'm aware you can control VDDCI smile.gif , like I said I don't think it is dummy feature on Tonga regarding VDDCI but is regarding MVDD. I am reading through the Tonga bios mod thread and few others as not been here redface.gif . Like I said I believe NCP81022 is controlling it as I think that is what is giving the monitoring data info to HWiNFO, I'm sure Mumak would confirm in his support thread.

It could well be that on RX 480 VDDCI is not controllable via that table, on Fiji it does nothing for VDDCI or MVDD. I lowered VDDCI in stages to a lot lower than 1000mV (~ -500mV) and card functioned as it should even with an OC on GPU/HBM. I know on Hawaii setting VDDCI -150mV from stock would give issues even when GPU was in idle state (ie 300MHz GPU / 150MHz RAM), IR3567B did control VDDCI on Hawaii though. The only thing that table in PowerPlay allows me to do on Fiji is add additional HBM clock states, search Fiji bios mod there is post with info/video.

I believe on Fiji most values in that table are populated just because something like a driver/app that accesses ROM needs to see something there and has a "issue" if they are zero'd/empty (not tested this yet). It maybe the same case on RX 480 as Fiji (ie VDDCI/MVDD = dummy , only RAM states/clocks function).
Edited by gupsterg - 9/4/16 at 9:19am
XPS - R7 1700
(14 items)
 
XPS - i5 4690K
(12 items)
 
XPS - Q6600
(8 items)
 
CPUMotherboardGraphicsRAM
Ryzen 7 1700 Asus Crosshair VI Hero Sapphire Fury X@1145/545 G.Skill Trident Z 2x 8GB 3200MHz C14 
Hard DriveCoolingCoolingCooling
Samsung Evo 840 ThermalRight Archon IB-E X2 + 2x TY143 ThermalRight TY-143 2x front case intake Arctic Cooling F12 + 2x F9 as rear case exhaust 
OSMonitorKeyboardPower
Win 7 Pro x64 / Win 10 Pro x64 Asus MG279Q Cherry MX-Board 3.0 Cooler Master V850 
CaseMouse
SilverStone TJ06 Logitech G700S 
CPUMotherboardGraphicsRAM
i5 4690K@4.9GHz 1.255V Asus Maximus VII Ranger Sapphire Fury X@1145/545 HyperX Savage 2x8GB 2400MHz C11 
Hard DriveCoolingOSMonitor
Samsung Evo 840 TR Archon SB-E X2 Win 7 Pro x64 / Win 10 x64 Asus MG279Q 
KeyboardPowerCaseMouse
Cherry MX-Board 3.0 Cooler Master V850 SilverStone TJ06 Logitech G700S 
CPUMotherboardGraphicsRAM
Intel Q6600 G0 Asus P5K Premium Black Pearl Sapphire Toxic HD5850 Corsair Dominator 4GB 
Hard DriveCoolingOSPower
Crucial MX 100 256GB TR TRUE Rev.A Win 7 Pro x64 Cooler Master V650 
  hide details  
Reply
XPS - R7 1700
(14 items)
 
XPS - i5 4690K
(12 items)
 
XPS - Q6600
(8 items)
 
CPUMotherboardGraphicsRAM
Ryzen 7 1700 Asus Crosshair VI Hero Sapphire Fury X@1145/545 G.Skill Trident Z 2x 8GB 3200MHz C14 
Hard DriveCoolingCoolingCooling
Samsung Evo 840 ThermalRight Archon IB-E X2 + 2x TY143 ThermalRight TY-143 2x front case intake Arctic Cooling F12 + 2x F9 as rear case exhaust 
OSMonitorKeyboardPower
Win 7 Pro x64 / Win 10 Pro x64 Asus MG279Q Cherry MX-Board 3.0 Cooler Master V850 
CaseMouse
SilverStone TJ06 Logitech G700S 
CPUMotherboardGraphicsRAM
i5 4690K@4.9GHz 1.255V Asus Maximus VII Ranger Sapphire Fury X@1145/545 HyperX Savage 2x8GB 2400MHz C11 
Hard DriveCoolingOSMonitor
Samsung Evo 840 TR Archon SB-E X2 Win 7 Pro x64 / Win 10 x64 Asus MG279Q 
KeyboardPowerCaseMouse
Cherry MX-Board 3.0 Cooler Master V850 SilverStone TJ06 Logitech G700S 
CPUMotherboardGraphicsRAM
Intel Q6600 G0 Asus P5K Premium Black Pearl Sapphire Toxic HD5850 Corsair Dominator 4GB 
Hard DriveCoolingOSPower
Crucial MX 100 256GB TR TRUE Rev.A Win 7 Pro x64 Cooler Master V650 
  hide details  
Reply
post #537 of 3354
Quote:
Originally Posted by gupsterg View Post

Warning: Spoiler! (Click to show)
No worries on info smile.gif , sorry for delayed response just been avoiding being on OCN as my PM inbox resembles like a mini forum for AMD bios mod requests and help redface.gif .

Yes, I'm aware you can control VDDCI smile.gif , like I said I don't think it is dummy feature on Tonga regarding VDDCI but is regarding MVDD. I am reading through the Tonga bios mod thread and few others as not been here redface.gif . Like I said I believe NCP81022 is controlling it as I think that is what is giving the monitoring data info to HWiNFO, I'm sure Mumak would confirm in his support thread.

It could well be that on RX 480 VDDCI is not controllable via that table, on Fiji it does nothing for VDDCI or MVDD. I lowered VDDCI in stages to a lot lower than 1000mV (~ -500mV) and card functioned as it should even with an OC on GPU/HBM. I know on Hawaii setting VDDCI -150mV from stock would give issues even when GPU was in idle state (ie 300MHz GPU / 150MHz RAM), IR3567B did control VDDCI on Hawaii though. The only thing that table in PowerPlay allows me to do on Fiji is add additional HBM clock states, search Fiji bios mod there is post with info/video.

I believe on Fiji most values in that table are populated just because something like a driver/app that accesses ROM needs to see something there and has a "issue" if they are zero'd/empty (not tested this yet). It maybe the same case on RX 480 as Fiji (ie VDDCI/MVDD = dummy , only RAM states/clocks function)
.

OK, thank you very much for the answer again thumb.gif
post #538 of 3354
So, if the Memory voltage control is a dummy feature in the reference RX480, why in GPU-Z (version 1.10.0) my VDDC shows a reduced value after doing some undevolt to the VRAM? also my GPU becomes unstable if i dont underclock the memory with that undervolt applied.
Edited by kaptain345 - 9/4/16 at 12:58pm
post #539 of 3354
Should be the memory controller voltage, same as Hawaii. The voltage for the Samsung K4G80325FB-HC25 on the ref-design is much higher:
http://www.samsung.com/semiconductor/products/dram/graphic-dram/gddr5-component/K4G80325FB?ia=759
http://forum.hwbot.org/showthread.php?t=160306
Edited by hellm - 9/4/16 at 3:28pm
post #540 of 3354
You can link to the mod bios noreference 480 4Gb?
New Posts  All Forums:Forum Nav:
  Return Home
  Back to Forum: AMD/ATI
Overclock.net › Forums › Graphics Cards › AMD/ATI › Polaris Bios Editing ( RX5xx / RX4xx )