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A temporary fix for the excess PCI-E slot power draw for the reference RX 480 cards - Page 2

post #11 of 178
Fixes something that isn't even a problem, hmmm.
The only real problem is the media blowing this way out of proportion.
post #12 of 178
thanks for the reply thumb.gif
Quote:
Originally Posted by The Stilt View Post

So these commands change the default configuration of the IR3567 VRM controller, which is used on all of the reference boards. There are six phases for the GPU power plane (VDDC) and half of these phases are fed from the PCI-E power connector and the other half from the PCI-E slot 12V source. At the default configuration the cards are shipped with, each of the VRM phases handle the same amount of load. The changes made by these commands affect how the load is distributed between the VRM phases.
Yes, I understand those basics.
However, Igor from Tom's Hardware deduced that actually 4 phases are connected to the slot and only 2(+1) to the 6-pin connector.

source (sorry, German): http://www.tomshardware.de/amd-radeon-rx-480-grafikkarte-leistungsaufnahme-pci-sig,testberichte-242143.html

This makes more sense, too, imho, when you say "each of the VRM phases handle the same amount of load", looking at the measured total power consumption. How can you be sure the balance is actually 50/50? I'm not trying to take a swipe at you, just trying to understand.
Also, how did you validate those results? Do you have equipment to measure the draw from PEG/PCIe 6 Pin?
Quote:
Originally Posted by The Stilt View Post

With the configuration enabled by these commands, the half of the VRM which is fed from the PCI-E power connector will be taking care of a larger portion of the load than the other half. Since the total power draw of the GPU will remain intact, the power draw from the PCI-E slot will decrease and the power draw from the PCI-E power connector will increase.
Yes, I thought that. But what I was searching for (out of curiosity) is what do the exact parameters mean? And how is the exact load distribution between the phases when choosing values from B to F. Can you split the command value and explain the single bits?
post #13 of 178
Thread Starter 
Quote:
Originally Posted by I-o-I View Post

thanks for the reply thumb.gif
Yes, I understand those basics.
However, Igor from Tom's Hardware deduced that actually 4 phases are connected to the slot and only 2(+1) to the 6-pin connector.

source (sorry, German): http://www.tomshardware.de/amd-radeon-rx-480-grafikkarte-leistungsaufnahme-pci-sig,testberichte-242143.html

This makes more sense, too, imho, when you say "each of the VRM phases handle the same amount of load", looking at the measured total power consumption. How can you be sure the balance is actually 50/50? I'm not trying to take a swipe at you, just trying to understand.
Also, how did you validate those results? Do you have equipment to measure the draw from PEG/PCIe 6 Pin?
Yes, I thought that. But what I was searching for (out of curiosity) is what do the exact parameters mean? And how is the exact load distribution between the phases when choosing values from B to F. Can you split the command value and explain the single bits?

I gave the instructions how to measure the VRM structure on RX 480 to a fellow Finnish hardware site author, who received the card for review. Based on the measurements he made based on my instructions the split is indeed 50/50 for the VDDC (GPU) power plane. The drains of the first three (of the green region) are connected together and connected to the PCI-E power connector. The drains of the lower three high-side fets are also connected together and connected to the PCI-E slot 12V pins.

The changes have been tested by w1zzard (TPU site author) who reported reduced PCI-E slot power draw with these settings.

The region highlighted in green are the high-side fets for the VDDC (GPU) power plane. The single high-side and low-side fet above these is for VDDCI (not affected). Also the picture you posted contains an error (besides the distribution). The phases go from 1-6 in descending order, not in ascending order.

post #14 of 178
Hell, this sounds like something AMD should implement as a fix.
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Bruce
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post #15 of 178
@The Stilt: alright, thanks for pointing that out.
@brucethemoose: and I expect them to.
post #16 of 178
Thread Starter 
Quote:
Originally Posted by I-o-I View Post

Yes, I thought that. But what I was searching for (out of curiosity) is what do the exact parameters mean? And how is the exact load distribution between the phases when choosing values from B to F. Can you split the command value and explain the single bits?

I forgot to answer (kind of) to this one.
The IR3567 is a 6+2 phase controller. There are eight control values (one for each phase) in total which determine the current imbalance between the phases. The second output (+2) is unused on RX 480 so that leaves us six effective control values. When the control values are all zero, each and every active phase will take care of an equal slice of the total load. That's the default configuration these cards are using. When any of these control values are programmed to any non zero (1-15) value, it means that the phase with this control value programmed will take care of a larger slice of the total load than the ones with the control value set to zero. In this case the control value has been programmed for phases 1, 2 and 3. Therefore phases 1 - 3 will do more work than phases 4 - 6. Since phases 1-3 are fed from the PCI-E power connector the load from the PCI-E slot will decrease.

Unfortunately I cannot disclose how the programming values are decoded, since that is IR confidential.
post #17 of 178
Okay, I understand that, of course.
Now, I'm satisfied, thank you very much thumb.gif
post #18 of 178
Thanks a lot for your effort.
Can you please explain how applying this fix directly on the BIOS would work?
Maybe we can include this function on the Polaris BIOS Editor: http://forums.guru3d.com/showthread.php?t=408469
post #19 of 178
thank you Stilt for posting this
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post #20 of 178
Most important question: Does it effect performance at stock or when overclocked?
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