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[Fudzilla]Kaby Lake conjures up two overclocking tricks - Page 9

post #81 of 95
I wonder if this chip can hit 5ghz and will it be soldered or same TIM ever since ivy bridge?
    
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post #82 of 95
Quote:
Originally Posted by prznar1 View Post

Quote:
Originally Posted by Dyson Poindexter View Post

I want to go the other way:

http://www.overclock.net/t/1515838/mini-dtx-hype-thread-itx-with-two-pcie-slots
hoh, you think that so dimm and 8x pcie would not help that? rolleyes.gif
there's merit to both approaches!
post #83 of 95
Quote:
Originally Posted by sherlock View Post

Quote:
Originally Posted by Yttrium View Post

This. I know skylake is supposed to be more consumer-end with their max of 4 cores (Which is awesome for single core performance) but with their I7 price tags I expected more than 16 lanes. 28 lanes like the 5820K had is enough for a x16 graphics card and then have 12 lanes over for whatever you need.

Skylake+Z170 have 20 PCIE 3.0 lanes, except you can only use 16 of them through the PCIE3.0 slots(for GPUs).

The other 4 is linked directly to the Chipset through DMI 3.0, So you can run a PCIE 3.0 X4 SSD in M.2 format linked to the chipset.

I thought it was 16x pcie3.0 directly to the CPU and an additional 20 pcie 3.0 lanes through the PCH.

http://www.pcper.com/reviews/Processors/Intel-Core-i7-6700K-Review-Skylake-First-Enthusiasts/Z170-Chipset-and-ASUS-Deluxe
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post #84 of 95
Quote:
Originally Posted by Cyro999 View Post

3.0x16 (even x8) doesn't really limit anything though, it's even less important than RAM overclocks.

Based on current trends, I'll probably keep my next computer as long as this sandy bridge, so some overkill in the PCIE department would be a plus.
post #85 of 95
Quote:
Originally Posted by serothis View Post

I thought it was 16x pcie3.0 directly to the CPU and an additional 20 pcie 3.0 lanes through the PCH.

This is true, but the PCH is connected to the CPU by DMI 3.0, which is essentially a slightly modified collection of four PCI-E 3.0 lanes.

So, it's 20 lanes from the CPU with four of those lanes dedicated to the PCH, which then acts as a switch/expander, more or less.

Depending on how you use the lanes connected to the CPU and PCI, this could have performance implications...anything that needs to reach outside the PCH or devices directly connected to the PCH will never surpass the available DMI bandwidth.
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post #86 of 95
Quote:
Originally Posted by Blameless View Post

Quote:
Originally Posted by serothis View Post

I thought it was 16x pcie3.0 directly to the CPU and an additional 20 pcie 3.0 lanes through the PCH.

This is true, but the PCH is connected to the CPU by DMI 3.0, which is essentially a slightly modified collection of four PCI-E 3.0 lanes.

So, it's 20 lanes from the CPU with four of those lanes dedicated to the PCH, which then acts as a switch/expander, more or less.

Depending on how you use the lanes connected to the CPU and PCI, this could have performance implications...anything that needs to reach outside the PCH or devices directly connected to the PCH will never surpass the available DMI bandwidth.

So what was it pre-z170?

According the pcper article I linked
Quote:
A close second in importance in my mind is the move to support up to 20x lanes of PCI Express 3.0 on the Z170 chipset! Compared to the Z87 and Z97 chipset that shipped with 8x lanes of PCIe 2.0, this is a dramatic improvement

8x pcei2.0 lanes has the same bandwidth as 4x pcie3.0 lanes. Which is the configuration I always thought it was.

Pcper makes it sound like it's 20 additional lanes, independent of the 16 direct to cpu lanes.
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post #87 of 95
Quote:
Originally Posted by serothis View Post

So what was it pre-z170?

Depends on the platform and chipset.

The lanes coming from the PCH depend on the PCH. The lanes coming from the CPU depend on the CPU.
Quote:
Originally Posted by serothis View Post

Pcper makes it sound like it's 20 additional lanes, independent of the 16 direct to cpu lanes.

It is 20 additional lanes, independent of the 16 lanes directly attached to the CPU.

However, the CPU to z170 bandwidth is still limited by the DMI 3.0 link, which is essentially PCI-E 3.0 4x and anything that needs to go through the CPU from the PCH has to to go through that link.

If you plug 20GB/s worth of I/O into you PCH and try to use it all at the same time, you'll almost certainly see a huge bottleneck at the DMI, unless the devices attached to the PCH are only talking to each other, and not accessing the CPU, system memory, or anything in the 16x lanes that are directly connected to the CPU.

This is why you can't (or at the very least, shouldn't) run multi-GPU configurations with a GPU plugged into the PCH...you get significantly more latency and only have 4x 3.0 lanes of bandwidth to the CPU (and thus the other card in the system), some of which is already utilized by other devices.
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post #88 of 95
4.8 ghz for masses?
post #89 of 95
Quote:
Originally Posted by Blameless View Post

Depends on the platform and chipset.

The lanes coming from the PCH depend on the PCH. The lanes coming from the CPU depend on the CPU.
It is 20 additional lanes, independent of the 16 lanes directly attached to the CPU.

However, the CPU to z170 bandwidth is still limited by the DMI 3.0 link, which is essentially PCI-E 3.0 4x and anything that needs to go through the CPU from the PCH has to to go through that link.

So, you're telling me that, for all the PCIe slots in an ATX motherboard, on Skylake, we've only got x20 lanes total? Just off the bat, the GPU takes x16! And, so, the other 5 PCIe slots, they're all fighting over x4?

Man, that's confused me for so long.

Well, thank you for clearing this up. I now understand how SLI works and why "tri-SLI" was always listed as x8 / x8 / x4. For the splitter/expander PCH setup, I guess it's happy to give out as many lanes as it wants, but if you try to maximize your devices, you'll be capped at x20.
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post #90 of 95
Quote:
Originally Posted by ikjadoon View Post

So, you're telling me that, for all the PCIe slots in an ATX motherboard, on Skylake, we've only got x20 lanes total? Just off the bat, the GPU takes x16! And, so, the other 5 PCIe slots, they're all fighting over x4?

Man, that's confused me for so long.

Well, thank you for clearing this up. I now understand how SLI works and why "tri-SLI" was always listed as x8 / x8 / x4. For the splitter/expander PCH setup, I guess it's happy to give out as many lanes as it wants, but if you try to maximize your devices, you'll be capped at x20.

You cannot run tri-SLI that way. SLI needs a minimum of x8.

To run tri or quad SLI on a Z170 board, you would need a PLX PEX8747. Granted, with Nvidia no longer supporting 3 and 4 way SLI in games, it is mostly for benchmarkers and they are better off using the HEDT platform. That's especially because high end boards with a PLX tend to be very expensive. I have noticed this generation that even boards that used to such as the Asus Z170 Maximus Extreme and the MSI Z170 XPower no longer have PLX chips. Gigabyte still does though, as does EVGA on the Z170 Classified.

Crossfire does run at x4 though. Even at PCIe 3.0 x4, the penalty isn't that bad.
https://www.techpowerup.com/reviews/AMD/R9_Fury_X_PCI-Express_Scaling/

So you could run x8/x8/x4 3-way Crossfire via the PCH. Granted it will be a bit less than x4, depending on what else uses that bandwidth.

Of course, this may not be a huge loss either way. Frame time tests show poor game scaling - save Crysis 3 and perhaps Battlefield 4.
http://www.pcper.com/reviews/Graphics-Cards/AMD-Fury-X-vs-NVIDIA-GTX-980-Ti-2-and-3-Way-Multi-GPU-Performance

So in that regard, the CryEngine and Frostbite Engines may be very good for multi-GPU.

This might change dramatically though with DX12, especially if Explicit Multi-Adapter gains steam (and most importantly it is split frame rendering, not alternate frame rendering, so frame times are improved, which is far more important that frame rates.


Quote:
Originally Posted by Oj010 View Post

For short bench sessions yes or a really good one, above average sample for 24/7 use, yes. Average samples hit around 4.5 to 4.6 GHz, some bad samples even as low as 4.4 GHz.

There seems to have been a clockspeed drop compared to Devil's Canyon. Granted, what we don't know is whose overclocks are super stable (ex: could pass Linpak, Prime95 Large FFTs, and the most stringent tests), versus whose are just "gaming stable". Assuming a similar proportion though, it does look like compared to the 4790K, there has been a drop in clock speeds by around 200 MHz, which erases a lot of the gains in IPC of the 6700K.

Top samples on the 4790K hit 4.9-5.0 GHz, but those aren't for everyday and require a delid to pass any serious stability test. Plus you gotta be really luck on the silicon lottery (or buy a binned chip). The era of single digit "sidegrades" has been on us for a while now.

Kind of sad that the DMI 3.0 and the new motherboard features are more exciting than the CPU itself.


Quote:
Originally Posted by Blameless View Post

However, the CPU to z170 bandwidth is still limited by the DMI 3.0 link, which is essentially PCI-E 3.0 4x and anything that needs to go through the CPU from the PCH has to to go through that link.

If you plug 20GB/s worth of I/O into you PCH and try to use it all at the same time, you'll almost certainly see a huge bottleneck at the DMI, unless the devices attached to the PCH are only talking to each other, and not accessing the CPU, system memory, or anything in the 16x lanes that are directly connected to the CPU.

This is why you can't (or at the very least, shouldn't) run multi-GPU configurations with a GPU plugged into the PCH...you get significantly more latency and only have 4x 3.0 lanes of bandwidth to the CPU (and thus the other card in the system), some of which is already utilized by other devices.


Yes, this is a huge bottleneck. X99 and platforms earlier are even worse off with DMI 2.0. I just wish that X99 had DMI 3.0, but it will have to wait for Skylake E.

Personally I'd argue that even DMI 3.0 is not enough and that more lanes need to be allocated to the PCH. This is especially true considering we now have motherboards that offer features like RAID for 3 M.2 disks. That will quickly bottleneck the DMI 3.0 interface.
Edited by CrazyElf - 7/11/16 at 5:30pm
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