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[Arstechinica] Transistors will stop shrinking in 2021, but Moore’s law will live on

post #1 of 46
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Quote:
Transistors will stop shrinking after 2021, but Moore's law will probably continue, according to the final International Technology Roadmap for Semiconductors (ITRS).

The ITRS—which has been produced almost annually by a collaboration of most of the world's major semiconductor companies since 1993—is about as authoritative as it gets when it comes to predicting the future of computing. The 2015 roadmap will however be its last.

The most interesting aspect of the ITRS is that it tries to predict what materials and processes we might be using in the next 15 years. The idea is that, by collaborating on such a roadmap, the companies involved can sink their R&D money into the "right" technologies.

For example, despite all the fuss surrounding graphene and carbon nanotubes a few years back, the 2011 ITRS predicted that it would still be at least 10 to 15 years before they were actually used in memory or logic devices. Germanium and III-V semiconductors, though, were predicted to be only five to 10 years away. Thus, if you were deciding where to invest your R&D money, you might opt for III-V rather than nanotubes (which appears to be what Intel and IBM are doing).

http://arstechnica.com/gadgets/2016/07/itrs-roadmap-2021-moores-law/
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post #2 of 46
Good thing transistors don't need to shrink to boost energy efficiency or FLOPS and/or IPS per watt. Examples include Westmere to Sandy Bridge (32nm), Bulldozer to Piledriver (32nm), and especially Kepler to Maxwell (28nm) in recent years. Same process, but slightly to dramatically improved efficiency at the same performance, or performance at the same power consumption (an obligatory "Bulldozer sucked" is appropriate here biggrin.gif).

Meanwhile there have been cases where smaller processes don't actually help much. When AMD ported K10 from 40nm to 32nm for Llano APUs, they had hit a wall and neither efficiency nor performance improved much. I'm not sure of other examples off the top of my head though, but a smaller process isn't inherently a cause higher performance or efficiency.
Edited by CynicalUnicorn - 7/25/16 at 11:25am
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post #3 of 46
So, basically what this article is stating is that:
Quote:
  • The 2015 roadmap will be the last roadmap published by the ITRS.
  • It will no longer be economically viable to shrink transistors after the year 2021.
  • Chip makers and designers will begin to move away from FinFET in 2019.
  • The next big design structure after FinFET is GAA (Gate-All-Around).
  • Following the introduction of GAA, transistors will become vertical instead of horizontal (This will allow for a massive increase in transistor density).
  • Then In 2024 we will hit a "hard thermal ceiling". (The only real solution is to completely rethink chip packaging and cooling).
  • The cut-off date for choosing which lithography / patterning techs will be used for commercial 7nm and 5nm logic chips is soon.
  • Currently manufacturers use increasing levels of multiple patterning. But two new fabrication methods are on the horizon (Extreme Ultraviolet (EUV) and Directed Self-Assembly (DSA)).
  • ITRS says if either technology is to be used over multiple patterning for 7nm logic, the they will need to proven in the next few months.

There are so many questions left unanswered here:

  1. How is this the "last" ITRS roadmap? Are they just postponing meeting / writing until after new technologies are discovered or what?
  2. FinFET is only going to be "mainstream" for 3 years and then trashed?
  3. What is the probability that EUV or DSA will actually be used for 7nm or 5nm production?

Also, the timeline doesn't really match-up for me. This roadmap is basically saying that once (if) we hit 3nm in 2024, that we will hit a hard thermal ceiling which will require us to "throw out" all current designs for packaged chips and start from scratch? I find quite a bit of this hard to believe, but the ITRS has been pretty spot-on in the past.

- Insan1tyOne redface.gif
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post #4 of 46
This is not to mention awkward unforseen issues with particular sizes, such as the 20nm debacle solved by FinFET and released as 16nm/14nm.

I don't think we will see a lot of movement for a while from these processes, as the main driver is mobile efficiency with low current/leakage to promote less battery consumption and not high frequency.

Will probably not be good for consumer GPUs, but fortunately with the GPU ML boom thanks to ImageNet, and bioinformatics for folding there might be incentive from a research perspective.
post #5 of 46
Node shrinks might not happen but all R&D will simply shift to yields for big die's. This does leave one to wonder what will happen to overclockers. Then again, the article mentioned the neverending thermal envelope and thats exactly what overclocking is about. So we still will be bickering over "overclocker's dream" chips after all.
post #6 of 46
Wow. So how exactly are we going to get better GPUs, especially for VR?

Last I heard, it takes 16k resolution to approximate what we see in reality, and current VR is only about 2kish @ 90 FPS (2160x1200)


That VR resolution will last for a long time if the difficulties of getting better performance in the future is true.
     
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post #7 of 46
Quote:
Originally Posted by ChronoBodi View Post

Wow. So how exactly are we going to get better GPUs, especially for VR?

Last I heard, it takes 16k resolution to approximate what we see in reality, and current VR is only about 2kish @ 90 FPS (2160x1200)


That VR resolution will last for a long time if the difficulties of getting better performance in the future is true.

Well, they did start talking about electronic blood to remove heat at the end there, so we have some room to go up. Maybe we can get a least 8K. specool.gif
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post #8 of 46
Giant stacked dies with some kind of liquid-cooling solution integrated directly into the chip's internals is the next likely thing in my opinion, at least for improving performance. I for one can't wait for a 5 megacore CPU in a 12-kilowatt TDP cube-of-death form factor.

It will also be a good time for some revolutions in the software industry. If mainstream hardware stops getting faster and faster, we'll finally have to prioritize library and framework optimization instead of being lazy because today's slow thing will be great on next year's CPU.
post #9 of 46
Quote:
Originally Posted by ChronoBodi View Post

Wow. So how exactly are we going to get better GPUs, especially for VR?

Last I heard, it takes 16k resolution to approximate what we see in reality, and current VR is only about 2kish @ 90 FPS (2160x1200)


That VR resolution will last for a long time if the difficulties of getting better performance in the future is true.

A Titan X (the first one, Maxwell rolleyes.gif) is something like 50% faster than a 780Ti/Titan Black, yet is built on a die just 7% larger (601mm2 vs 561mm2). Same 28nm TSMC process node. Alternatively, we can look at AMD. The 359mm2 Tonga die is about 2% larger than Tahiti at 352mm2 and, while it performs about the same and contains the same amount of stream processors and compute units, crams 700 million more transistors into that space, bringing it from 4.3 billion to 5 billion.

Of course, both of those examples allocate transistors very differently. Both Tahiti and GK110 have improved FP64 ratios for compute, while Tonga and GM200 lack it entirely past the barebones ratio the architectures use for compatibility's sake. Additionally, Tonga has a narrower memory bus at just 256-bit rather than 384-bit. But regardless of how they're allocated, the transistor density still increased after a couple years' work despite no new process whatsoever.

Hmm, I think a spreadsheet of microarchitecture vs transistors/mm2 is in order. I don't think original GCN's and Kepler's densities were too different back in 2012.
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post #10 of 46
Well I would imagine we'll also see a big leap in performance with the shrinking motherboard...meaning DDR4 will become on-die memory components for the CPU...aka HBM...that'll bring a big performance jump and concentration of data... I would also imagine PCIE will become optimized for additional bandwidth...then not only that but the south/north bridge will see massive improvements which will greatly improve performance there also... win win. rolleyes.gif
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