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[Arstechinica] Transistors will stop shrinking in 2021, but Moore’s law will live on - Page 2

post #11 of 46
EUV is definitely something interesting, as it will help sharpen up the edges. The tech required to generate and harness the 13nm light is no small feat. The source for the light is drops of molten tin, that are hit with one laser to puff them up and increase their volume and then a second laser which causes them to emit 13nm light. The light is then captured and redirected toward the patterning equipment. The hard part is that the drops of tin aren't all the same size, and they aren't all in the same place in the stream. So you have to adjust the orientation of the lasers in order to make sure you zap the tin drops properly so you can maintain uniform illumination. Having dips in the intensity of the light source is bad for process control for the patterning, so the requirements really are tight.

However, even with DUV, you eventually hit a limit. Keep in mind that a 7nm-wide strip of metal is all of eighteen atoms wide. 3nm, and you're at seven or eight atoms wide. There just isn't that much more room to go down.
post #12 of 46
Quote:
Originally Posted by Yttrium View Post

Node shrinks might not happen but all R&D will simply shift to yields for big die's. This does leave one to wonder what will happen to overclockers. Then again, the article mentioned the neverending thermal envelope and thats exactly what overclocking is about. So we still will be bickering over "overclocker's dream" chips after all.

You will have software provided by Intel or AMD that benchmarks the cpu and set the frequency accordingly. No vcore adjustments or bus clock increases. This cpu can run to that frequency and that's it. PERIOD!!! CPU lottery will have a whole new meaning.
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post #13 of 46
Quote:
Originally Posted by CDub07 View Post

Quote:
Originally Posted by Yttrium View Post

Node shrinks might not happen but all R&D will simply shift to yields for big die's. This does leave one to wonder what will happen to overclockers. Then again, the article mentioned the neverending thermal envelope and thats exactly what overclocking is about. So we still will be bickering over "overclocker's dream" chips after all.

You will have software provided by Intel or AMD that benchmarks the cpu and set the frequency accordingly. No vcore adjustments or bus clock increases. This cpu can run to that frequency and that's it. PERIOD!!! CPU lottery will have a whole new meaning.

Please no! anything but the Vcore!
post #14 of 46
Quote:
Originally Posted by CDub07 View Post

You will have software provided by Intel or AMD that benchmarks the cpu and set the frequency accordingly. No vcore adjustments or bus clock increases. This cpu can run to that frequency and that's it. PERIOD!!! CPU lottery will have a whole new meaning.
It has already began with cpu turbo and gpu boost
post #15 of 46
Quote:
Originally Posted by ChronoBodi View Post

Wow. So how exactly are we going to get better GPUs, especially for VR?

Last I heard, it takes 16k resolution to approximate what we see in reality, and current VR is only about 2kish @ 90 FPS (2160x1200)


That VR resolution will last for a long time if the difficulties of getting better performance in the future is true.

Move away to something other than a CMOS transistor. That is where R&D will move to.

There will always be contam in fabs and process margins that fab tools shift into that cause yield loss but that's not R&D worthy.
post #16 of 46
We'll probably see some kind of light computing or DNA computing by 2024, so even if the semiconductors hit a road block, computing power will still grow.
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post #17 of 46
Quote:
Originally Posted by ChronoBodi View Post

Wow. So how exactly are we going to get better GPUs, especially for VR?

Last I heard, it takes 16k resolution to approximate what we see in reality, and current VR is only about 2kish @ 90 FPS (2160x1200)


That VR resolution will last for a long time if the difficulties of getting better performance in the future is true.
they probably gonna improve density & yield on larger die.

Remember when Athlon XP, or Pentium 3 die size is about 70mm-100mm square only, much smaller than todays CPU's die.

I figure we are going to go wider, bigger die size b4 we move on newer technology
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post #18 of 46
Quote:
Originally Posted by Clocknut View Post

they probably gonna improve density & yield on larger die.

Remember when Athlon XP, or Pentium 3 die size is about 70mm-100mm square only, much smaller than todays CPU's die.

I figure we are going to go wider, bigger die size b4 we move on newer technology

yup, they'll just resort to finding "cheaper" ways to manufacture bigger dies.
post #19 of 46
Quote:
Originally Posted by Insan1tyOne View Post

So, basically what this article is stating is that:
There are so many questions left unanswered here:

  1. How is this the "last" ITRS roadmap? Are they just postponing meeting / writing until after new technologies are discovered or what?
  2. FinFET is only going to be "mainstream" for 3 years and then trashed?
  3. What is the probability that EUV or DSA will actually be used for 7nm or 5nm production?

Also, the timeline doesn't really match-up for me. This roadmap is basically saying that once (if) we hit 3nm in 2024, that we will hit a hard thermal ceiling which will require us to "throw out" all current designs for packaged chips and start from scratch? I find quite a bit of this hard to believe, but the ITRS has been pretty spot-on in the past.

- Insan1tyOne redface.gif

Don't know #1 or 2, but #3... I'd bet nearly anything that EUV is ready by 7nm. Multipass lithography (current gen as mentioned in the article) makes the entire process more cumbersome; longer manufacturing times due to the necessity to get tricky with how you protect various structures, higher resource use (more steps to make chips = more gasses/chems/ect) not to mention more opportunity for yield loss.

Edit: actually, not sure what wavelength they're using right now for 14/16nm, but not even sure it's tight enough to pattern a 7nm feature? Tight might be the wrong word. Physically possible?
Edited by asuindasun - 7/25/16 at 6:37pm
post #20 of 46
Quote:
Originally Posted by asuindasun View Post

Edit: actually, not sure what wavelength they're using right now for 14/16nm, but not even sure it's tight enough to pattern a 7nm feature? Tight might be the wrong word. Physically possible?

My understanding is that the current wavelength isn't short enough to pattern even 16nm, that is why you have to do multipatterning. I believe 7nm is possible with the current wavelength but with even more multis in the multipattern.

I must say directed self-assembly (DSA) sounds like much cooler tech. How far away are seeds for an i7? What do you need to water them with? biggrin.gif
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