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[AT] AMD Zen Microarchitecture: Dual Schedulers, Micro-Op Cache and Memory Hierarchy Revealed - Page 12

post #111 of 233
Quote:
Originally Posted by one-shot View Post

I get all of that. I just expected a 6700k to perform better by a larger degree with those minor differences.

When your limitation is on the GPU, of course there won't be a lot of differences. Many of the small differences you see are due to the playthrough not being exactly the same, or an update to the game causing slightly different performance, updated drivers causing slightly different performance, etc. In very few instances there will be dramatic differences. Keep in mind a 10% performance difference at 60 FPS is a 6 FPS difference.
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post #112 of 233
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Originally Posted by AmericanLoco View Post

I really love the armchair electrical engineers here. Uh huh, yeah, I'm sure a 14nm Excavator would absolutely destroy Zen. That's why AMD went through the trouble of designing a new core from scratch, right?

AMD took a gamble will Bulldozer, but lost since highly threaded applications didn't start (and still haven't) showed up. It's simple, if the Bulldozer architecture could be made to work, they would have done so. It can't, so they're throwing it out.

There are plenty of well threaded applications and even games around these days. That's not the reason bulldozer family failed. Main reason was that CMT the way it was implemented by AMD was sacrificing way too much ST performance in order to get extra cores in the same die area. Intel on the other hand could keep good ST performance and achieve good MT scaling using SMT with minimal die space investment. For a design as BD to be competitive AMD needed to have the upper hand in lithography tech, it was that broken. Ofc it was Intel that had the better foundry so it ended up a bloodbath. Zen is SMT because AMD learned their lesson.
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post #113 of 233
Quote:
Originally Posted by Kuivamaa View Post
 
Quote:
Originally Posted by AmericanLoco View Post

I really love the armchair electrical engineers here. Uh huh, yeah, I'm sure a 14nm Excavator would absolutely destroy Zen. That's why AMD went through the trouble of designing a new core from scratch, right?

AMD took a gamble will Bulldozer, but lost since highly threaded applications didn't start (and still haven't) showed up. It's simple, if the Bulldozer architecture could be made to work, they would have done so. It can't, so they're throwing it out.

There are plenty of well threaded applications and even games around these days. That's not the reason bulldozer family failed. Main reason was that CMT the way it was implemented by AMD was sacrificing way too much ST performance in order to get extra cores in the same die area. Intel on the other hand could keep good ST performance and achieve good MT scaling using SMT with minimal die space investment. For a design as BD to be competitive AMD needed to have the upper hand in lithography tech, it was that broken. Ofc it was Intel that had the better foundry so it ended up a bloodbath. Zen is SMT because AMD learned their lesson.

AMD did with the BD uArch what Intel did with Netburst, they relied on high clocks to overcome the low IPC performance of their chips. Though in this case BD isn't nearly as bad as Netburst was, Netburst had a 40% cache miss rate, which caused AMD's chips with half the clock speed to crush the best Intel could muster. Fortunately AMD learned the same lesson Intel did, that this just doesn't work and have thus implemented a special cache just for this. I hope neither go down this route again for the foreseeable future.

 

Quote:

Originally Posted by Cyro999 View Post
 
Quote:
Skylake so far has been a disappointment with a regression of performance at times, it's only two advantages are DDR4 and being able to clock higher than Haswell.

Uh, source on that?

Skylake is a bit faster than Haswell for most loads - not a lot faster, but a bit. Something like 13% IIRC for x264, around the 10% per-clock for most tasks.. I'm not aware of any notable regressions.

Side benefits were dramatically lower temperatures (like 25c lower than first gen haswell), more consistent overclocks and a great memory controller for 3200-4000mhz ddr4

 

 

Quote:
Originally Posted by one-shot View Post
 
Quote:
Originally Posted by Cyro999 View Post

Uh, source on that?

Skylake is a bit faster than Haswell for most loads - not a lot faster, but a bit. Something like 13% IIRC for x264, around the 10% per-clock for most tasks.. I'm not aware of any notable regressions.

Side benefits were dramatically lower temperatures (like 25c lower than first gen haswell), more consistent overclocks and a great memory controller for 3200-4000mhz ddr4

I just recently went to Anandtech Bench and looked up 2600k vs 6700k and was surprised at the gaming results. There isn't much of a difference in the many games they tested. Some games even show 2600k performing better, which makes no sense.

It's in a thread somewhere on these forums that shows very little performance gains and in fact, at times, a performance regression. This is to be expected as Skylake is no different than what nVidia have done, release the same old chip on a new process with slight tweaks such as DDR4.

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post #114 of 233
Quote:
Originally Posted by Seronx View Post




Do the math;
P-State FID 0x16 - VID 0x10 - IDD 15 (19.00x - 1.450 V) // 3.8 GHz @ 1.45v // 10.51 watts
P-State FID 0x10 - VID 0x2E - IDD 11 (16.00x - 1.262 V) // 3.2 GHz @ 1.262v // 13.51 watts <-- 1.25v
P-State FID 0xD - VID 0x3E - IDD 9 (14.50x - 1.162 V) // 2.9 GHz @ 1.162v // 10.11 watts <-- 1.15v
P-State FID 0xB - VID 0x46 - IDD 8 (13.50x - 1.112 V) // 2.7 GHz @ 1.112v // 8.57 watts <-- 1.1v
P-State FID 0x7 - VID 0x58 - IDD 6 (11.50x - 1.000 V) // 2.3 GHz @ 1v // 5.8 watts
P-State FID 0x114 - VID 0x66 - IDD 4 (9.00x - 0.912 V) // 1.8 GHz @ 0.912v // 3.83 watts <-- 0.9v
P-State FID 0x10C - VID 0x6E - IDD 3 (7.00x - 0.862 V) // 1.4 GHz @ 0.862v // 2.76 watts <-- 0.85v
FX-9800P on GF28HPA.

FDSOI just literally shoots up. 22FDX products would be ready for Mid-2017/Late-2017. Then, you have all 20LPM/14XM Architectural improvements for Bulldozer as well. FP256, Adders in the AGLUs, 2x32B Load/1x32B Store per Integer core, massive amounts of auto-route/auto-place improvements with new EDA tools. If 22FDX then FBB+6T SRAM can replace 8T SRAM. Massive areal improvement in the L1i/L1d for Bulldozer right there. L2 can be given 64B/c perf which would destroy Zen's 32B/c.

 

 

Right okay, you lost me completely in the bolded part.

 

If Zen is the next architecture, why would they bother improving on Bulldozer derivates anymore and port them to 22/20/14nm nodes?

 

Re. automated tooling, it was said that it was one of the reasons Phenom didn't match Core in efficiency and overall performance, the general wasted space. This AFAIK wasn't improved until well into Bulldozer, and even then the level of refinement still hasn't been said to match the A64s.

 

Cache speeds were also quoted one of the reasons a branch misprediction was so deadly for BD and in reality this was said to happen quite often, but you stilll have the issue of the front end not being fast enough to feed the rest of the module under 100% load, which has been said to be improved on, but again, no reports of this not being longer the case.

 

In case I am misunderstanding what you've said, would you mind using words instead of letters to describe terms? Will make it easier for someone who isn't digesting node feature sildes all day long :)

   
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post #115 of 233
Quote:
AMD did with the BD uArch what Intel did with Netburst, they relied on high clocks to overcome the low IPC performance of their chips. Though in this case BD isn't nearly as bad as Netburst was, Netburst had a 40% cache miss rate, which caused AMD's chips with half the clock speed to crush the best Intel could muster. Fortunately AMD learned the same lesson Intel did, that this just doesn't work and have thus implemented a special cache just for this. I hope neither go down this route again for the foreseeable future.


You make it sound like NETBURST was so bad and AMD was so perfect. I was a Northie, Prescott, and an P4 Extreme Edition Gallatin user at one point. Things were not as bad given that in multi-media, INTEL was not too far behind. In games, however, things were a bit different.

You are also ignoring, on purpose I assume, the fact that AMD had ODMC in their design, allowing them to have greater instruction handling. Someone who you may not know, Paul Otellini, once said that ODMC, which later became IMC on INTEL, is a one off improvement which was delayed until the whole pipeline was overhauled. Hence the birth of E6600 Conroe, a 250 dollar chip, sending a 1000 dollar chip to hide in same tongue.gif.


I am all for praising AMD but let us not cross a line where we blindly say how good AMD is but ignore certain facts.
Edited by Wishmaker - 8/19/16 at 1:49am
 
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post #116 of 233
Quote:
Originally Posted by Wishmaker View Post


You make it sound like NETBURST was so bad and AMD was so perfect.

 

Willamette failed to match 180nm and 130nm Tualatin in overall performance, performance per clock, performance per watt, performance per dollar and overall platform cost.

 

Northwood was a bit faster, but still horrible in performance per watt vs. Tualatin. Gallatin was faster because it finally managed to reach decent clockspeeds, not without its tremendous power consumption though.

 

 

Prescott->Presler were just pretty much irrelevant compared to Athlon64 and their TDPs in comparison to A64 chips was proportionally as bad as Skylake i5 vs FX-8350.

 

So yes, it was atrocious.

   
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post #117 of 233
Quote:
Originally Posted by looniam View Post

instead of multi quoting:

AMD cannot price zen close to intel no matter how competitive their chips are; they still have a bad reputation left from bulldozer and will need much lower pricing to entice apprehensive buyers (read OEMs).

These aren't mindless gamers and marketing, people buying server CPU's will weight all pro's and cons regardless of amd's "reputation"
post #118 of 233
Quote:
Originally Posted by Artikbot View Post

If Zen is the next architecture, why would they bother improving on Bulldozer derivates anymore and port them to 22/20/14nm nodes?
Zen is perfect for replacing 14h/16h (Bobcat/Jaguar) core families. It is however not perfect for replacing 15h (Bulldozer) core families.
Quote:
Originally Posted by Artikbot View Post

Re. automated tooling, it was said that it was one of the reasons Phenom didn't match Core in efficiency and overall performance, the general wasted space. This AFAIK wasn't improved until well into Bulldozer, and even then the level of refinement still hasn't been said to match the A64s.
Automation hasn't been an issue at all. Agena/10h was bad because 65nm PDSOI was using a LP transistor implant to reduce costs. Anything else is because the architecture didn't meld well with the node. Core as a whole has higher computational and memory throughput than K8-derived architectures. Which gives Core the advantage of running lower clocks. It also had the advantage of being Low Power on High Performance nodes. While, AMD was High Performance on Low Power.
Quote:
Originally Posted by Artikbot View Post

Cache speeds were also quoted one of the reasons a branch misprediction was so deadly for BD and in reality this was said to happen quite often, but you stilll have the issue of the front end not being fast enough to feed the rest of the module under 100% load, which has been said to be improved on, but again, no reports of this not being longer the case.
Mispredicts will always be an issue. Bulldozer derived isn't any worse off from Zen or Sandy Bridge to Skylake. If it doesn't hit the L0 instruction cache [Loop/Micro-op Buffer] then it will hit L1 instruction cache which is 15 cycles(Sandy)/16 cycles(Bulldozer)/18 cycles(Zen). The front-end in Bulldozer/Piledriver provided enough instructions. Four macro-ops equal 4 computational[Reg-ALU-Reg] and 4 load+store ops[Reg-Mem/Mem-Reg].

Bulldozer:
15 cycle mispredict (branch in-pipe/pick stage)
16 cycle mispredict (branch in L1 instruction cache)
20 cycle mispredict (branch in L2 unified cache)

Zen:
9-13 cycle mispredict (branch in L0 instruction cache)
17 cycle mispredict (branch in-pipe/pick stage)
18 cycle mispredict (branch in L1 instruction cache)
22 cycle mispredict (branch in L2 unified cache)

Branches are very unlikely to hit L2 cache (~32KB). While Jumps will almost always go to memory(~32MB).

----
Quote:
FDSOI just literally shoots up. 22FDX products would be ready for Mid-2017/Late-2017. Then, you have all 20LPM/14XM Architectural improvements for Bulldozer as well. FP256, Adders in the AGLUs, 2x32B Load/1x32B Store per Integer core, massive amounts of auto-route/auto-place improvements with new EDA tools. If 22FDX then FBB+6T SRAM can replace 8T SRAM. Massive areal improvement in the L1i/L1d for Bulldozer right there. L2 can be given 64B/c perf which would destroy Zen's 32B/c.
Fully Depleted Silicon on Insulator, literally has a dynamic/adaptive voltage frequency scale that shoots up. The 22 nanometer Fully Depleted [X being Base Platform /+Ultra Low Power components /+Ultra High Performance components /+Radio Frequency and Analog components /+Ultra Low Leakage components] 1.0 physical design kit is expected to allow for production releases for Mid-2017 to Late-2017. The 22nm FDSOI node allows for vastly more improved EDA tools over FinFET nodes which means faster and denser designs with the same macros.

For the shrink to 22nm FDSOI that particular 15h architecture gets all the Bulldozer architectural improvements from 20 nanometer Low Power Mobility slash 14nm Extreme Mobility versions. Which I have found to be Full 256-bit Vectors/Loads/Stores, Complex Arithmetic Logic Units instead of Simple Arithmatic Logic units in the Address Generating Logic Units, 2x 32 byte loads and 1x 32 byte stores per L1 data cache which just happens to be per core.

If 22nm FDX is used then six transistor SRAM with forward body bias can replace eight transistor SRAM. Which means more advanced improvements can be applied to the cores and floating point unit, and lastly the front-end. This would be allowed with the shift from 8T SRAM to 6T SRAM+FBB in the L1 instruction cache and L1 data caches. The overall added area shrink might even allow for a double bandwidth boost to the L2 unified cache.
Edited by Seronx - 8/19/16 at 3:22am
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AMD FX ~Seronx
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post #119 of 233
People, please don't read seronx' posts, most of the time he has no idea what he's talking about, i did the mistake to follow his posts in the steamroller thread....he's mostly making wild assumptions with limited information
post #120 of 233
Quote:
Originally Posted by kevinf View Post

I think based on AMD's history, https://en.wikipedia.org/wiki/List_of_AMD_FX_microprocessors
an 8 core monster should be ~ $400
You know that AMD started the 1000$ ''Enthusiast'' CPU ? If Zen can compete with current Intel's offering , they are going to price it competitively, just like they do with their GPUs.
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