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[AT] AMD Zen Microarchitecture: Dual Schedulers, Micro-Op Cache and Memory Hierarchy Revealed - Page 13

post #121 of 233
Quote:
Originally Posted by Wishmaker View Post

You make it sound like NETBURST was so bad and AMD was so perfect. I was a Northie, Prescott, and an P4 Extreme Edition Gallatin user at one point. Things were not as bad given that in multi-media, INTEL was not too far behind. In games, however, things were a bit different.

You are also ignoring, on purpose I assume, the fact that AMD had ODMC in their design, allowing them to have greater instruction handling. Someone who you may not know, Paul Otellini, once said that ODMC, which later became IMC on INTEL, is a one off improvement which was delayed until the whole pipeline was overhauled. Hence the birth of E6600 Conroe, a 250 dollar chip, sending a 1000 dollar chip to hide in same tongue.gif.


I am all for praising AMD but let us not cross a line where we blindly say how good AMD is but ignore certain facts.

Netburst wasn't bad

it was horrible compared to AMDs come back cpu at the time.
post #122 of 233
Quote:
Originally Posted by Seronx View Post


Zen is perfect for replacing 14h/16h (Bobcat/Jaguar) core families. It is however not perfect for replacing 15h (Bulldozer) core families.
Automation hasn't been an issue at all. Agena/10h was bad because 65nm PDSOI was using a LP transistor implant to reduce costs. Anything else is because the architecture didn't meld well with the node. Core as a whole has higher computational and memory throughput than K8-derived architectures. Which gives Core the advantage of running lower clocks. It also had the advantage of being Low Power on High Performance nodes. While, AMD was High Performance on Low Power.
Mispredicts will always be an issue. Bulldozer derived isn't any worse off from Zen or Sandy Bridge to Skylake. If it doesn't hit the L0 instruction cache [Loop/Micro-op Buffer] then it will hit L1 instruction cache which is 15 cycles(Sandy)/16 cycles(Bulldozer)/18 cycles(Zen). The front-end in Bulldozer/Piledriver provided enough instructions. Four macro-ops equal 4 computational[Reg-ALU-Reg] and 4 load+store ops[Reg-Mem/Mem-Reg].

Bulldozer:
15 cycle mispredict (branch in-pipe/pick stage)
16 cycle mispredict (branch in L1 instruction cache)
20 cycle mispredict (branch in L2 unified cache)

Zen:
9-13 cycle mispredict (branch in L0 instruction cache)
17 cycle mispredict (branch in-pipe/pick stage)
18 cycle mispredict (branch in L1 instruction cache)
22 cycle mispredict (branch in L2 unified cache)

Branches are very unlikely to hit L2 cache (~32KB). While Jumps will almost always go to memory(~32MB).

----
Fully Depleted Silicon on Insulator, literally has a dynamic/adaptive voltage frequency scale that shoots up. The 22 nanometer Fully Depleted [X being Base Platform /+Ultra Low Power components /+Ultra High Performance components /+Radio Frequency and Analog components /+Ultra Low Leakage components] 1.0 physical design kit is expected to allow for production releases for Mid-2017 to Late-2017. The 22nm FDSOI node allows for vastly more improved EDA tools over FinFET nodes which means faster and denser designs with the same macros.

For the shrink to 22nm FDSOI that particular 15h architecture gets all the Bulldozer architectural improvements from 20 nanometer Low Power Mobility slash 14nm Extreme Mobility versions. Which I have found to be Full 256-bit Vectors/Loads/Stores, Complex Arithmetic Logic Units instead of Simple Arithmatic Logic units in the Address Generating Logic Units, 2x 32 Byte Load and 1x 32 Byte store per L1 data cache which is per core.

If 22nm FDX is used then six transistor SRAM with forward body bias can replace eight transistor SRAM. Which means more advanced improvements can be applied to the cores and floating point unit, and lastly the front-end. This would be allowed with the shift from 8T SRAM to 6T SRAM+FBB in the L1 instruction cache and L1 data caches. The overall added area shrink might even allow for a double bandwidth boost to the L2 unified cache.

 

Okay that makes more sense now, cheers.

 

The last paragraph is possibly the most interesting point IMO. Even if they decided to stay on the exact same design, the reduction in die space would translate to better yields therefore possibly better prices.

 

Still I don't think a transition to 22nm node is going to be a thing. And it is unlikely AMD will ever release information with enough detail to the general public to know what they are or aren't using.

 

Quote:
Originally Posted by Marios145 View Post

People, please don't read seronx' posts, most of the time he has no idea what he's talking about, i did the mistake to follow his posts in the steamroller thread....he's mostly making wild assumptions with limited information

 

I wouldn't say they're assumptions. Mostly speculation from what a node could potentially offer. Since we don't know what is or isn't being used, it's only fair you at least read what he has to say.


Edited by Artikbot - 8/19/16 at 3:26am
   
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post #123 of 233
Quote:
Originally Posted by Yttrium View Post

Warning: Spoiler! (Click to show)
Quote:
Originally Posted by looniam View Post

instead of multi quoting:

AMD cannot price zen close to intel no matter how competitive their chips are; they still have a bad reputation left from bulldozer and will need much lower pricing to entice apprehensive buyers (read OEMs).

These aren't mindless gamers and marketing, people buying server CPU's will weight all pro's and cons regardless of amd's "reputation"

but i am talking about "mindless gamers." nice of you to ignore that.
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post #124 of 233
Quote:
Originally Posted by mus1mus View Post

I need to buy me some popcorns!

And coffee. Tons of.
\\

This will be a long day of a read, I sense!.

tongue.gif

Hear, hear! Off to get a refill smil3dbd4e4c2e742.gif
     
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post #125 of 233
Quote:
Originally Posted by Artikbot View Post

I wouldn't say they're assumptions. Mostly speculation from what a node could potentially offer. Since we don't know what is or isn't being used, it's only fair you at least read what he has to say.
It's not even speculation, it's just nonsense. He just throws tons and tons of jargon and gibberish together without actually knowing what he's talking about - his posts read like randomly copied and pasted bits and pieces from semiconductor datasheets. Notice he had no rebuttal for my rebuttal of his claims of Zen having worse/same energy-per-instruction than Excavator? He tried to defend himself with some nonsense about clock speeds and core count, which is irrelevant when talking about per core instructions and energy per cycle.

If you look around, you'll find the real semiconductor engineers on here and elsewhere. They don't fill their posts with tons of technical jargon pretending to be more knowledgeable than they are.

AMD has a lot of very smart engineers working for them, and they had arguably one of the best in the business leading the Zen design. If the BD architecture could have been fixed, they would have had it fixed by now. You don't start a whole new design from scratch if your existing design is salvageable. BD is a dead end, and Excavator is its magnum opus.
post #126 of 233
Quote:
Originally Posted by TheLAWNOOB View Post

Now imagine a 4Ghz Skylake in a laptop.

It's the i7 6820HK.

http://ark.intel.com/products/88969/Intel-Core-i7-6820HK-Processor-8M-Cache-up-to-3_60-GHz

lachen.gif

Overclocking doesn't count, obviously, when comparing to a theoretical stock part.
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post #127 of 233
Quote:
Originally Posted by one-shot View Post

I just recently went to Anandtech Bench and looked up 2600k vs 6700k and was surprised at the gaming results. There isn't much of a difference in the many games they tested. Some games even show 2600k performing better, which makes no sense.

Anand usually biases their game benchmarks to be GPU-bound on purpose and their benchmark database isn't perfect. I'm not aware of any significant regressions from even Haswell to Skylake (let alone sandy bridge) and the expectation is Skylake running some 30% faster than Sandy in most CPU limited games, it's more in a few niche ones.
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post #128 of 233
Quote:
Originally Posted by KyadCK View Post

Quote:
Originally Posted by TheLAWNOOB View Post

Now imagine a 4Ghz Skylake in a laptop.

It's the i7 6820HK.

http://ark.intel.com/products/88969/Intel-Core-i7-6820HK-Processor-8M-Cache-up-to-3_60-GHz

lachen.gif

Overclocking doesn't count, obviously, when comparing to a theoretical stock part.

I'm not comparing it. Even a 2.5 Ghz Skylake will beat 3Ghz Zen no problem.

I just wanted you to imagine how nice it would be. Besides the power consumption.
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post #129 of 233
Quote:
Originally Posted by TheLAWNOOB View Post

I'm not comparing it. Even a 2.5 Ghz Skylake will beat 3Ghz Zen no problem.

I just wanted you to imagine how nice it would be. Besides the power consumption.

Sure.
post #130 of 233
Quote:
Originally Posted by Cyro999 View Post

Quote:
Originally Posted by one-shot View Post

I just recently went to Anandtech Bench and looked up 2600k vs 6700k and was surprised at the gaming results. There isn't much of a difference in the many games they tested. Some games even show 2600k performing better, which makes no sense.

Anand usually biases their game benchmarks to be GPU-bound on purpose and their benchmark database isn't perfect. I'm not aware of any significant regressions from even Haswell to Skylake (let alone sandy bridge) and the expectation is Skylake running some 30% faster than Sandy in most CPU limited games, it's more in a few niche ones.

An inconvenient truth.

https://www.techpowerup.com/forums/threads/skylake-i7-6700k-lose-to-haswell-i7-4790k-in-gaming.215004/
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