Originally Posted by AmericanLoco
I'm sure a 14nm Excavator would absolutely destroy Zen. That's why AMD went through the trouble of designing a new core from scratch, right?
In the case of a 20nm/14nm 15h architecture, it wouldn't be 14nm Excavator. The valid nomenclature would be NG2 Bulldozer, if no codename was offered.
Bulldozer => Bulldozer
Enhanced Bulldozer => Piledriver
Next-Gen Bulldozer => Steamroller
Enhanced Next-gen Bulldozer => Excavator
Next-Gen 2 Bulldozer => ???
The reason for the trouble of designing a new core from scratch could be ANYTHING.
Originally Posted by AmericanLoco
AMD took a gamble will Bulldozer, but lost since highly threaded applications didn't start (and still haven't) showed up. It's simple, if the Bulldozer architecture could be made to work, they would have done so. It can't, so they're throwing it out.
Bulldozer works better with lightly threaded applications this is do to higher clocks than Intel/AMD Jaguar. The issue was heavily threaded applications which could thrash execution units, L1i, L1d, and L2. There is really only two workloads memory(MLP/memory-level-parallelism) and execution(IPC/instructions-per-cycle), which are divided by energy(EPI/energy-per-instruction).
Stoney Ridge replacing Carrizo-L/Beema/Kabini is all the proof needed. If you running a lightweight browser which is faster a 2 GHz core @ 15Ws or a 3.5 GHz core @ 15Ws?
AMD has pointed out there is no EPI improvement between Zen(GF14LPP) and Excavator(GF28A). Except, Excavator(GF28HPA) has a 10% EPI improvement over Excavator(GF28A).
AMD has fully taken the wraps off its brand new seventh generation APU architecture Bristol Ridge, which it announced earlier this year. It promises users around a 20-percent boost in CPU performance and a 37-percent boost in GPU performance over Bristol Ridge's predecessor Carrizo, which launched in 2015.
"We didn't change the shape of the transistor, but we changed transistor implant and gave the transistor much more mobility," explained Macri to Ars. "At any given voltage, we get more current out. It's typically what you'd call a process variant. GlobalFoundries did a great piece of work here. We basically got an extra 200MHz or so out of the core, for a nice 10 percent boost in performance, which is greater than what you typically get out of a simple process tweak. But this wouldn't have made a new product. I wouldn't be calling this a seventh generation product if all we did was get this."
There is also the FIVR in Bristol/Stoney but apparently AMD pulled a Skylake and Zen doesn't have a FIVR;
This paper describes modeling and implementation of a fully digital integrated linear voltage regulation system implemented in a 28nm x86-64 core to reduce power gating entry or exit latency. Running on a 100 MHz clock, the controller samples voltage using a time-to-digital converter, and controls a set of PFETs organized in a ring topology around the CPU cores to drop voltage down to a specified target value. A simple analytical model is developed and validated through fast Matlab-Simulink simulation, enabling quick design turnaround and reducing schedule impact.
The regulation system is designed to support input-output voltages in the range 1.3 V - 0.55 V. Digitally-controlled header resistance values range from 1.5 Ω to 2 mΩ. Stable processor behavior is observed down to 0.6 V, enabling fast pseudo-power gating entry and exit. In a high-performance x86-64 dual-core microprocessor chip, the controller enables an effective 6% frequency increase for lightly threaded applications by increasing the boost state residency.
Signals; We are launching this new architecture look at it! LOOK AT IT! *Meanwhile behind the scenes* When is GlobalFoundries going to get to 1.0 PDK for 22FDX so we can Pentium M ourselves.Edited by Seronx - 8/18/16 at 7:42pm