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[Anandtech] Early AMD Zen Server CPU and Motherboard Details: Codename ‘Naples’, 32-cores, Dual Socket Platforms, Q2 2017

post #1 of 16
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Quote:
At the AMD Zen microarchitecture announcement event yesterday, the lid was lifted on some of the details of AMD’s server platform. The 32-core CPU, codename Naples, will feature simultaneous multithreading similar to the desktop platform we wrote about earlier, allowing for 64 threads per processor. Thus, in a dual socket system, up to 128 threads will be available. These development systems are currently in the hands of select AMD partners for qualification and development.

AMD was clear that we will expect to hear more over the coming months (SuperComputing 2016 is in November 2016, International SuperComputing is in June 2017) with a current schedule to start providing servers in Q2 2017.

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Edited by jeffdamann - 8/19/16 at 6:24pm
    
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post #2 of 16
Who wants to bet it's a G34-style dual die chip? thumb.gif

They're almost certainly cheaper than Intel's big, monolithic dies, but I've never figured out if there's any performance hit because of that. There probably is, related to cache I'm sure, but it doesn't seem that Zen has a unified LLC at all (opting for multiple L3 caches per "block" of four cores, a bit like the L2 in the consoles' SoCs) so that might be moot.
Edited by CynicalUnicorn - 8/19/16 at 11:59am
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post #3 of 16
If the indications on the board are true, AMD is taking the ARM64 dump and returning to PC64 with a vengance.

The signs are those sockets are holding 8 channel memory chips, even if it's two 4 channel chips per die its still massive bandwidth.
post #4 of 16
I just hope they make a good choice on the networking. Can't exactly slump there from a enterprise grade board. I'm hoping that they swallow their pride and use Intel chips there instead of Broadcom or Realtek, or any other chip.
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post #5 of 16
Quote:
Originally Posted by CynicalUnicorn View Post

Who wants to bet it's a G34-style dual die chip? thumb.gif

They're almost certainly cheaper than Intel's big, monolithic dies, but I've never figured out if there's any performance hit because of that. There probably is, related to cache I'm sure, but it doesn't seem that Zen has a unified LLC at all (opting for multiple L3 caches per "block" of four cores, a bit like the L2 in the consoles' SoCs) so that might be moot.

Even if the dies are split up, I wonder if that would even have any real world impact on performance. I'm sure lots of threads share resources, but how often does one thread need to share resources with tons of other threads? The only experience I have with multi-threaded programming is creating a server program that has a thread for each connection in a distributed system, so I'm honestly not sure how common resource sharing between cores is.

Hopefully the latency penalty is low enough and rare enough that it doesn't really cause any issues.
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post #6 of 16
Can't wait to start hearing clock speeds, heck, can't wait for Zen! Obviously early ES were impressive enough for Apple and a couple of others, couple that with the last few days, and it looks promising.

Real excitement comes to mobile if Zen as an architecture truly does compete with Intel. Where does that place an AMD Zen laptop APU w/ a little HBM2 in terms of cost and performance? AMD could potentially flatten Pascal in laptops and be lower cost, or provide better margins to the manufacturers.
    
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post #7 of 16
Quote:
Originally Posted by CynicalUnicorn View Post

Who wants to bet it's a G34-style dual die chip? thumb.gif

They're almost certainly cheaper than Intel's big, monolithic dies, but I've never figured out if there's any performance hit because of that. There probably is, related to cache I'm sure, but it doesn't seem that Zen has a unified LLC at all (opting for multiple L3 caches per "block" of four cores, a bit like the L2 in the consoles' SoCs) so that might be moot.

Intel's own QPI runs at 9.6GT/s (38.4GB/s) on modern Broadwell-E chips. HyperTransport, if AMD keeps using it, is capable of 25.6GB/s on the last known specification. SB-E was also 25.6GB/s.

Just compare two SB-E Quadcores to a single Octacore of similar speed, that should more or less give you the idea of it.
Quote:
Originally Posted by wolfej View Post

Quote:
Originally Posted by CynicalUnicorn View Post

Who wants to bet it's a G34-style dual die chip? thumb.gif

They're almost certainly cheaper than Intel's big, monolithic dies, but I've never figured out if there's any performance hit because of that. There probably is, related to cache I'm sure, but it doesn't seem that Zen has a unified LLC at all (opting for multiple L3 caches per "block" of four cores, a bit like the L2 in the consoles' SoCs) so that might be moot.

Even if the dies are split up, I wonder if that would even have any real world impact on performance. I'm sure lots of threads share resources, but how often does one thread need to share resources with tons of other threads? The only experience I have with multi-threaded programming is creating a server program that has a thread for each connection in a distributed system, so I'm honestly not sure how common resource sharing between cores is.

Hopefully the latency penalty is low enough and rare enough that it doesn't really cause any issues.

It can, but the OS will try to keep things "inside" the CPU where possible, and most programs that rely on mass threading don't talk to one another often.
Quote:
Originally Posted by bucdan View Post

I just hope they make a good choice on the networking. Can't exactly slump there from a enterprise grade board. I'm hoping that they swallow their pride and use Intel chips there instead of Broadcom or Realtek, or any other chip.

That isn't an AMD decision.

AMD creates the chipset and specification, and board partners (Dell, SuperMicro, Tyan, etc) make the boards. They can be as cheap or expensive as they like.
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post #8 of 16
Being a SoC seems really good for power efficiency. Shaving even a few watts off is a fair bit in low power systems, and adds up in large servers and supercomputers.
post #9 of 16
Quote:
Originally Posted by KyadCK View Post

Intel's own QPI runs at 9.6GT/s (38.4GB/s) on modern Broadwell-E chips. HyperTransport, if AMD keeps using it, is capable of 25.6GB/s on the last known specification. SB-E was also 25.6GB/s.

Just compare two SB-E Quadcores to a single Octacore of similar speed, that should more or less give you the idea of it.

Right, but that's two dies in two sockets. AMD is offering two dies on a single package, I assume with a connection similar to HBM's interposer? I'm not actually sure of the mechanics of MCMs. But I don't know about performance hits for sure and I haven't seen any benchmarks ever. AMD's current servers are perfect for testing though. 8 cores can be achieved with 1 or 2 sockets, each with 1 or 2 dies, using Bulldozer or Piledriver cores.
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post #10 of 16
Quote:
Originally Posted by CynicalUnicorn View Post

Right, but that's two dies in two sockets. AMD is offering two dies on a single package, I assume with a connection similar to HBM's interposer? I'm not actually sure of the mechanics of MCMs. But I don't know about performance hits for sure and I haven't seen any benchmarks ever. AMD's current servers are perfect for testing though. 8 cores can be achieved with 1 or 2 sockets, each with 1 or 2 dies, using Bulldozer or Piledriver cores.

Two dies per package works like two dies in two sockets. The organic carrier (PCB the chips are soldered to) has part of the interconnects tied together so that in a 1P layout it ends up being logically 2P and in a 2P it is like a 4P. Intel did this back in the Core 2 days (Core 2 Quad & Xeon) and AMD has been doing it since the Phenom II era (Opteron only).
Edited by KarathKasun - 8/19/16 at 5:03pm
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