Originally Posted by nrpeyton
There are so many different theories out there regarding the correct calculation for tRAS.
So far I've heard:
- tRAS = CAS (tCL) + tRCD (sum of first two primary timings only)
- tRAS = CAS (tCL) + tRCD + tRP (sum of the three main primary timings)
- tRAS = CAS (tCL) + tRCD + tRTP (and this one which I just learnt today).
The most common
misconception seems to be that it's the sum of the first three primary timings. But anyone who knows anything at all should know this can't possibly be true. You just need to look at ratings for almost any kit out there.
So why so many guides across the internet are instructing people of that -- I do not know!
guides are mostly guesses... Timing rules are ... rules. The jedec document discusses the timing windows. like I said, cas+rcd_rtp = ras, +/- 2 since some MBs may have an offset. Low values may not actually run the bios value, since dram training will correct the timing error (and not report it to the OS, so you will not see the substituted value). The correction can only do so much.. then the system will either not boot or fail rigorous ram stability testing like HCi memtest or GSAT. Be sure to do more than simple AID64 Memtest, which is only one measure of ram performance. There are others.
as an example (burst = 4, tRTP= 6 clocks, tRAS = sum of cas, rcd. rtp +/- 2 )
Remember - a bad ram OC, unlike a bad cpu OC kindly which bsods, can result in a slow but steady corruption of the OS - to the point where it wil be unrecoverable.
more importantly, your ram sticks are training RTL and IOL values for channel B that are waaaay off. try increasing VSA slightly and monitor RTL values. They should either be the same or B=A+1. Eg, 52/53 and 7/7. You can set these manually. If 52/53 and 7/7 fails, try 52/53 and 7/8. Lower RTLs increase performance significantly (round trip latency).
From a real ram guy:Raja:
"No need for tRAS at 30. It's below the minimum time so the chipset will have to resort to some arbitrary timing. tRCD is the time it take to latch the row and transfer the data into the sense amps. CAS is the time it takes to find the column address have have the data ready for burst. Adding those two together brings you to 30 clocks. Each burst is 4 clock cycles in length. That brings you to 34. However, tRTP is set to 10. Which means that 40 clocks must elapse before tRAS elapses and the precharge command can be sent to transfer the data in the sense amps back into the dram cells. The minimum proper tRAS value for your setup is therefore 40 clocks.
All of the timings follow the same laws as DDR3 for minimum value, apart from tRRD_L which has a minimum spacing of 6 clocks
tRAS is the minimum time the row should be active. The row needs to be active for the entire duration it takes to perform tRCD, CAS and tRTP. Any lower and the chipset has to apply the minimum value arbitrarily - there may be an additional penalty for the collision as well.
So while it may look nice in screenshots to set tRAS to some low value (below the min threshold) in reality it is not helping and may be worse than setting the correct minimum value instead on relying on the IMC to correct the timing issue.
It that example, the rig was running below 40. And yeah, Of course you can run chipset minimums (I do frequently for benchmarks) but they are only stable to the specific benchmark running (eg, like 4000 12-12-12-28-1t, tho even in this case tRTP is 4, so it is still in play
)Edited by Jpmboy - 10/17/17 at 5:51pm