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Kaby Lake Overclocking Guide [With Statistics] - Page 445

post #4441 of 4773
Quote:
Originally Posted by becks View Post

You might want to lower your tRAS to increase Copy and/or decrease latency..I'd go as low as 26-28 with it...
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post #4442 of 4773
@nrpeyton

NVM cheers.gif
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post #4443 of 4773
Quote:
Originally Posted by becks View Post

@nrpeyton

NVM cheers.gif

There are so many different theories out there regarding the correct calculation for tRAS.

So far I've heard:
  1. tRAS = CAS (tCL) + tRCD (sum of first two primary timings only)
  2. tRAS = CAS (tCL) + tRCD + tRP (sum of the three main primary timings)
  3. tRAS = CAS (tCL) + tRCD + tRTP (and this one which I just learnt today).

The most common misconception seems to be that it's the sum of the first three primary timings. But anyone who knows anything at all should know this can't possibly be true. You just need to look at ratings for almost any kit out there.

So why so many guides across the internet are instructing people of that -- I do not know!
Edited by nrpeyton - 10/17/17 at 11:36am
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post #4444 of 4773
Quote:
Originally Posted by nrpeyton View Post

!

I personally have not went trough any online guides and just did it in a haste true self testing ... my main goal was to have it running asap.
Not the best at patient ...still telling myself everyday that I should push it just a bit more..but never really find the time to do it..always in a rush..
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post #4445 of 4773
Im surprised that swaping msi gaming 7 for asus Code , is such a big memory oc loss.
With msi able to boot at 3700
With code not eve 3400 boots ... strange mb thats the reason it was open box?smile.gif
Edit: after setting the timings manually, it boots at 3600 for now , will continue testing
Edited by MaKeN - 10/17/17 at 6:43pm
post #4446 of 4773
Quote:
Originally Posted by nrpeyton View Post

There are so many different theories out there regarding the correct calculation for tRAS.

So far I've heard:
  1. tRAS = CAS (tCL) + tRCD (sum of first two primary timings only)
  2. tRAS = CAS (tCL) + tRCD + tRP (sum of the three main primary timings)
  3. tRAS = CAS (tCL) + tRCD + tRTP (and this one which I just learnt today).

The most common misconception seems to be that it's the sum of the first three primary timings. But anyone who knows anything at all should know this can't possibly be true. You just need to look at ratings for almost any kit out there.

So why so many guides across the internet are instructing people of that -- I do not know!

guides are mostly guesses... Timing rules are ... rules. The jedec document discusses the timing windows. like I said, cas+rcd_rtp = ras, +/- 2 since some MBs may have an offset. Low values may not actually run the bios value, since dram training will correct the timing error (and not report it to the OS, so you will not see the substituted value). The correction can only do so much.. then the system will either not boot or fail rigorous ram stability testing like HCi memtest or GSAT. Be sure to do more than simple AID64 Memtest, which is only one measure of ram performance. There are others.

as an example (burst = 4, tRTP= 6 clocks, tRAS = sum of cas, rcd. rtp +/- 2 )



Remember - a bad ram OC, unlike a bad cpu OC kindly which bsods, can result in a slow but steady corruption of the OS - to the point where it wil be unrecoverable.

more importantly, your ram sticks are training RTL and IOL values for channel B that are waaaay off. try increasing VSA slightly and monitor RTL values. They should either be the same or B=A+1. Eg, 52/53 and 7/7. You can set these manually. If 52/53 and 7/7 fails, try 52/53 and 7/8. Lower RTLs increase performance significantly (round trip latency).

From a real ram guy:
Raja:
"No need for tRAS at 30. It's below the minimum time so the chipset will have to resort to some arbitrary timing. tRCD is the time it take to latch the row and transfer the data into the sense amps. CAS is the time it takes to find the column address have have the data ready for burst. Adding those two together brings you to 30 clocks. Each burst is 4 clock cycles in length. That brings you to 34. However, tRTP is set to 10. Which means that 40 clocks must elapse before tRAS elapses and the precharge command can be sent to transfer the data in the sense amps back into the dram cells. The minimum proper tRAS value for your setup is therefore 40 clocks.
All of the timings follow the same laws as DDR3 for minimum value, apart from tRRD_L which has a minimum spacing of 6 clocks

tRAS is the minimum time the row should be active. The row needs to be active for the entire duration it takes to perform tRCD, CAS and tRTP. Any lower and the chipset has to apply the minimum value arbitrarily - there may be an additional penalty for the collision as well.
So while it may look nice in screenshots to set tRAS to some low value (below the min threshold) in reality it is not helping and may be worse than setting the correct minimum value instead on relying on the IMC to correct the timing issue.
"

It that example, the rig was running below 40. And yeah, Of course you can run chipset minimums (I do frequently for benchmarks) but they are only stable to the specific benchmark running (eg, like 4000 12-12-12-28-1t, tho even in this case tRTP is 4, so it is still in play wink.gif )
Edited by Jpmboy - 10/17/17 at 5:51pm
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post #4447 of 4773
4000, 12, 12, 12 - 28

omg...

what voltage do you need to run that?
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post #4448 of 4773
Quote:
Originally Posted by nrpeyton View Post

4000, 12, 12, 12 - 28

omg...

what voltage do you need to run that?

If you have a good set of b-die modules, then 4000 12-12-12-28-220-1T, can be achieved with approx. 1.88-1.92 Dram volts and approx. 1.25-1.27 io and sa voltages..
Lesser quality modules may need between 1.94 - 1.98 Dram volts and a higher IO maybe upto 1.3 volts and higher SA upto 1.38 volts.

It also depends on your board, as some boards such as the MOCF overvolt automatically and you can set a lower voltage in the bios and the board will compensate.

Boards like Asus for example, require higher voltages to be put in the bios as they do not overvolt as much.

Samsung B-die can handle voltages as high as 2.10 DRAM volts for benching purposes.
Edited by tknight - 10/18/17 at 2:01am
post #4449 of 4773
Quote:
Originally Posted by Jpmboy View Post


What would be the minimum default for my little z170 platform than ?
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post #4450 of 4773
Quote:
Originally Posted by tknight View Post


If you have a good set of b-die modules, then 4000 12-12-12-28-220-1T, can be achieved with approx. 1.88-1.92 Dram volts and approx. 1.25-1.27 io and sa voltages..
Lesser quality modules may need between 1.94 - 1.98 Dram volts and a higher IO maybe upto 1.3 volts and higher SA upto 1.38 volts.

It also depends on your board, as some boards such as the MOCF overvolt automatically and you can set a lower voltage in the bios and the board will compensate.

Boards like Asus for example, require higher voltages to be put in the bios as they do not overvolt as much.

Samsung B-die can handle voltages as high as 2.10 DRAM volts for benching purposes.

And would you only apply that voltage to a DDR4 module under LN2? I assume there is less chance of destroying the module at voltages as high as that if under LN2?

(I have used Dry Ice before (but only on CPU) and I run my loop on an Acquarium Water Chiller- but can't get LN2 here in Scotland as it's not available at a pheasable price due to distance to nearest company that sells it). Also my DDR4 modules aren't part of my chilled water loop.

I know the maximum voltage for a DDR4 XMP certification is 1.5v (which I also use as my own maximum 24/7 DDR4 voltage). Are there people on this thread going higher than 1.5v for 24/7 on DDR4?
Edited by nrpeyton - 10/18/17 at 4:22am
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