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VRM on the new AM4 motherboards - Page 138

post #1371 of 1989
Quote:
Originally Posted by PsyM4n View Post

According to the documents you pointed to, the particular combination of nikos low and high side fets perform slightly better than the TI fets you pointed to. The numbers on these documents say so.

The difference here is minimal though. In practice, the difference would only affect extreme scenarios (ie: ln2, phase, etc) or scenarios when more than one low and/or high side fets are used per coil.
You can call me whatever you want. The fact is that errors happen. You might be doing the same thing perfectly fine for decades and still encounter a problem or two at some point. When that happens, it might not even be your fault.

I don't want to beat a dead horse but the PK616BA is a slower part than the TI NexFET let alone the other high side mosfets being used.
PK616BA has a turn on delay of 27 ns @ V_GS = 10V vs 8 ns on the TI NexFET @V_GS = 4.5V. (7ns for 4C09N and 4C10N @ V_GS=10V , max is 16ns for SM4337 @ V_GS = 10V)
Then there's the other specs such as rise time: 23ns at V_GS = 10 V vs 10ns of the NexFET rated at V_GS = 4.5 V. (28 ns for 4C09N @ V_GS=10 V , 26 ns for 4C10N @ V_GS=10 V , max is 9ns for SM4337 @ V_GS = 10V)
To add to that further there's a 51nS turnoff delay vs 33ns on the TI NexFET. (4C09N = 20ns @ V_GS = 10V , 18 ns for 4C10N @ V_GS=10 V , max is 37ns for SM4337 @ V_GS = 10V)
Then there's 24nS fall time , the TI NexFET has 4.7ns. (4C09N and 4C10N = 4ns @ V_GS = 10V , max is 14ns for SM4337 @ V_GS = 10V)
For all of those specs the PK616BA is basing off V_GS=10V , which is faster than V_GS = 4.5V.

Stepping down from V_DS = 15V to V_GS = 10V is less of a delta versus V_GS 4.5V.
Couple the fact that there are six of them (high side) in total for the CPU on the Xpower versus 8 phases on the CH VI Hero.
Thermal resistance junction to case is 4 °C/W vs the 2 °C/W of the NexFETs and for high side mosfets this directly limits you along with the dynamic characteristics.

When you are talking about the low side FETs, the PK632BA might have 88A on top of the paper but the heat dissipated is going to cook it : the package limitation is 40A and the thermal resistance junction to case is 2.7 °C/W vs the 2 °C/W of the NexFETs. Then there's a RDS(on) that has a max of 4mΩ , which is double that of the NexFETs (i.e. 8 phases of NexFETs ~~16 phases of PK632BA).

I'm just curious what led you to make such bold claims that the Xpower's mosfets were even close to the NexFETs. If they were so great I'd think the Intel MSI Xpower boards would use them.

I was honestly (pleasantly) surprised ASUS used NexFETs on the X370 Prime Pro instead of 4C09N or 4C10N plus 4C06N. On the mainstream Intel Z170/Z270 boards those were used, likely for cost savings.
Edited by AlphaC - 5/2/17 at 10:12pm
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post #1372 of 1989
Quote:
Originally Posted by PsyM4n View Post


As long as you have freedom of speech, you are free to your opinion, no matter what the said opinion is.

So according to you, if I come and visit there, rape you, beat you and cut your limbs off, it'll be your fault if you get offended, despite what I might have done to you. You're free to think like that and I'm free to disagree.

 

Yes - willingly taking a neutral stance, clinging to theoretical slim chances and deliberately using vagueness to boost one's credibility equals physical abuse and torture.

 

Very well done, 10/10 would use as an example again.

 

 

And yes, I'd love to see your performance estimations, numbers, sources and outcomes.

   
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post #1373 of 1989
OK. It's quite simple actually.

- The higher the frequency, the higher the losses. So I didn't even consider checking the switching timings. It's not even relevant in this case IMO.

- Packages integrating both low and high side fets have lower footprint, lower losses, more efficiency, because of their design.

- Packages integrating both low and high side fets dissipate the lost heat less efficiently cause the whole package works more (recent fairchild drmos even have metal on top of the package too, to help with that).

- Individual fets have less efficiency and more losses and yet dissipate heat more efficiently cause the package works less.

- A 1plus1 configuration of the nikos fets in question might be generating more heat but also dissipates more heat. Still the dissipation doesn't keep up with the heat generated from the losses. The TI fet in question is unquestionably better in this regard.

Because of very specific power requirements from the CPU it's possible to put much less load on each fet by doing a 2plus1 configuration for vcore, without actually increasing your phases, as msi did. By doing this you have even less heat generated and keep the power output high, assuming you have the means to get the heat away from the fets fast enough... by using a big heatsink with a big heatpipe for example.
What I'm saying here is that I considered the above, checked the boards in question, checked how the fets in question perform on their spec sheets and concluded that this particular approach on the titanium should perform slightly better than the asus prime using a single ti fet per phase.

That's pretty much it.
post #1374 of 1989
Still open to do an apples to apples comparison using a setup that may be common to noob OCers or non-enthusiasts using reasonable/realistic voltages. 1.4Vcore and 1.1VSoC in a closed case with no fan on the VRM, but with the side panel off to take measurements / feel the heatsink.
post #1375 of 1989
Quote:
Originally Posted by PsyM4n View Post

OK. It's quite simple actually.

- The higher the frequency, the higher the losses. So I didn't even consider checking the switching timings. It's not even relevant in this case IMO.

 

'IMO' doesn't apply when talking about fact. At 500kHz (more or less the average switching frequency for these) switching losses are definitely in the region where you start to account for them. Calculating them isn't easy, you need a lot of parameters from the FET as well as the converter topology.

 

More transistors also means higher switching losses.

 

 

Quote:
- Packages integrating both low and high side fets have lower footprint, lower losses, more efficiency, because of their design.

- Packages integrating both low and high side fets dissipate the lost heat less efficiently cause the whole package works more (recent fairchild drmos even have metal on top of the package too, to help with that).

 

Not strictly true. Integration is often out of convenience. I'd (and like myself, many others) much rather use a single monolithic package than several discrete elements. Saves time speccing them out, saves time laying down the PCB, saves time thinking about the thermals. Also simplifies the supply chain.

 

Of course, if you go with high end monolithic converters (such as PowIRstage), you get performance befitting of the segment they're targetting.

 

Quote:
- Individual fets have less efficiency and more losses and yet dissipate heat more efficiently cause the package works less.

- A 1plus1 configuration of the nikos fets in question might be generating more heat but also dissipates more heat. Still the dissipation doesn't keep up with the heat generated from the losses. The TI fet in question is unquestionably better in this regard.

 

No, not really. Cheap transistors have worse performance than integrated parts. You can spend the money (something MSI didn't do) and you will get striking performance, very much superior to what you can get with standard off-the-shelf monolithic

packages when it comes to high current applications.

 

And it doesn't matter how much heat a particular package can dissipate if you can't remove it from the thing to begin with - that's where thermal resistance for the package and the heatsink come to play. MSI did account for this and made use of a better heatsink. Gigabyte especially went with a more efficient design at low voltages and did away with a less capable heatsink. Unfortunately for us of course.

 

Quote:
Because of very specific power requirements from the CPU it's possible to put much less load on each fet by doing a 2plus1 configuration for vcore, without actually increasing your phases, as msi did. By doing this you have even less heat generated and keep the power output high, assuming you have the means to get the heat away from the fets fast enough... by using a big heatsink with a big heatpipe for example.

 

Yes - but only if you use equally high end parts, which MSI skipped. They did increase the number of switches on board - for obvious reasons, and it does the job.

Quote:

What I'm saying here is that I considered the above, checked the boards in question, checked how the fets in question perform on their spec sheets and concluded that this particular approach on the titanium should perform slightly better than the asus prime using a single ti fet per phase.

That's pretty much it.

 

They are both hugely overkill and limited by the heatsink, not the packages anyway. As are all mid-high end X370 boards.

 

Plus - it better perform better than the X370 Prime. It's the cheapest X370 board available, by a reasonable margin; while the MSI is the most expensive, also by a reasonable margin.

 

 

 

I see no numbers...

   
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post #1376 of 1989
Quote:
Originally Posted by bardacuda View Post

Still open to do an apples to apples comparison using a setup that may be common to noob OCers or non-enthusiasts using reasonable/realistic voltages. 1.4Vcore and 1.1VSoC in a closed case with no fan on the VRM, but with the side panel off to take measurements / feel the heatsink.

It will be a while before mine goes back into a case , if ever - one thing to remember is that an open case system on water has almost no airflow over the VRMS if it were in a properly configured case , it would most likely have more airflow over the heatsink surface..


Titanium on p5 with airflow on the vrms



Baracudas ASUS prime pro.





I more or less matched your settings for the IBT maximum run except that I was running 4ghz vs your 3850 and I was running 2933mhz on the ram vs your 2400.

The Titanium's maximum was 14 C cooler on the cpu VRM and it actually passed the test.
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post #1377 of 1989
Quote:
Originally Posted by Artikbot View Post

I see no numbers...

There is a reason for that. For numbers, more information is required. Exact thermal capabilities of the heatsink and the thermal pad and the board itself. Otherwise, any exact number will be wrong. Best you can do is rough estimation.

As for integration, apart from cost saving which is the primary reason, the closer the better, on same package it's even better, as long as your parts do not work at the same time. Which is precisely why it's the best approach for mosfets.

Quote:
Originally Posted by Artikbot View Post

More transistors also means higher switching losses.

Tell me you're kidding. No, seriously.
Edited by PsyM4n - 5/2/17 at 10:08am
post #1378 of 1989
Ok so not apples to apples then.

I am seeing 51°C in the first motherboard section which is what I was going by for my VRM temps. That would be a 6°C difference. I can't compare to the other sections with "VR1" and "VR2" as I don't have them on this board, and I can't see all of yours either, just the first two. I know I have one choke that tends to run much hotter than the other 5, so I assume the associated 'fet for that phase is also higher. I could skew results by only pointing at the two coolest running phases if I wanted.

This is why I would like to take video using IR thermometer / touch test for a comparison. Can't really trust software. And I'm not saying you're doing any funny business either, orkin. Let me be clear on that. It's just that if we want to put all this argument spam to bed then we need some standard test that would be difficult to fudge.
post #1379 of 1989
Quote:
Originally Posted by PsyM4n View Post

The guy here quoted multiple posts from multiple pages back just to tell me that I fell into a trap "like nobody else".... cause you know, this is war and such. Who needs to have an adult conversation when you can just say "I win, you lose, conversation ended" or something.
You could just tell us. It'll be interesting to see how the board responds to load changes. This is one of the few reasonable posts in the last pages.

You are the one beating yourself, that "trap" was set on your own..

Definitely not a war, I even gave you directions on what not to read ( absolute maximums ) in the datasheets, who's on a war is going to provide the enemy with intel ?

I hope you realize that most people on here have that mindset of always trying to share and educate and that is really nice. I often to do the same but I may like to have some fun while I prove a point.

You are not my enemy.

Enjoy the board, it is a really nice place to learn a new thing everyday - I do thumb.gif
Edited by virpz - 5/2/17 at 11:41am
post #1380 of 1989
Quote:
Originally Posted by PsyM4n View Post

Quote:
Originally Posted by bardacuda View Post

I see no numbers...

Umm....I never said that.
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