Originally Posted by teh-yeti
Since the R3 line is supposed to be quad cores with no SMT, do you think that the APUs will feature SMT? Or an L3 cache like the rest of the Ryzen line up?
I suspect the APUs will still have L3 cache, perhaps halved to 4MB though.
The loss of L3 in previous APUs (Construction and Stars cores) wasn't as painful because it was both slow and existing alongside a relatively large L2 cache. Zen's L3 (within CCX) is lower latency, and it's L2 cache much smaller.
Despite many things being disabled in Intel's budget (core-based) Pentium line, they still leave a reasonable 3MB L3 cache for 2 cores.
I suspect that performance on 'Core' and Zen would drop substantially if the L3 were completely disabled, although I don't recall this ever being simulated.