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ROG Crosshair VI overclocking thread - Page 1136

post #11351 of 17583
Ashes of the Singularity benchmark gives me a bsod with 121 bclk.
post #11352 of 17583
Quote:
Originally Posted by dorbot View Post

Correct me if I am wrong, but....
It seems to me that there is a growing consensus among us, that the approach GSkill have taken to communicate RGB data to and from the SPD modules over the SMbus is at fault and it is rendering very expensive RAM useless by corrupting vital SPD data. The idea may be sound if executed correctly / carefully but I think we all know the true situation there.
Its a total mess.

That's right. Due to such a wrong design decision I believe the manufacturer should accept these RMAs.
post #11353 of 17583
Quote:
Originally Posted by Mumak View Post

That's right. Due to such a wrong design decision I believe the manufacturer should accept these RMAs.
Doesn't GSkill have a lifetime warranty?
post #11354 of 17583
Anyone running Ryzen with Hynix DBL-Sided? I have an old kit of DDR4 2666 Hynix that did C13-14-14 at 1.315V. ( 8x8GB on X99 ). Been having some bizzare stability issues even with running it at 2666 C15 flat 1.315V...
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post #11355 of 17583
Quote:
Originally Posted by dorbot View Post


Did you turn off the lighting effects when you took this reading? It is among the known issues.

You should go into the BIOS as there is a section which displays the SPD without the software interference of a SMBus scan.
Edited by FloppyDrive - 4/24/17 at 11:33pm
post #11356 of 17583
Quote:
Originally Posted by FloppyDrive View Post

Doesn't GSkill have a lifetime warranty?

They do.

But they could turn around and say you caused the SPD data corruption. See links in this post.
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post #11357 of 17583
Quote:
Originally Posted by Mumak View Post

That's right. Due to such a wrong design decision I believe the manufacturer should accept these RMAs.

This is what my report looks like: https://drive.google.com/open?id=0B4hoXY-91SDFcmxwRGhKN2h4b2c

How can I get the .dbg files by the way? From what I can understand it looks like I lost all XMP info on one stick. Used the Aura software only (not the G.Skill one).
Edited by Clukos - 4/24/17 at 11:51pm
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post #11358 of 17583
Quote:
Originally Posted by Reikoji View Post

I theorize that if your CPU gets hot enough to throttle during the run your score will drop, tho I could be wrong. I've tried runs at higher (and fairly unsafe /w LLC4) voltages for 4200mhz and ended up with pretty darn high temp and lower score than 4150mhz with safer voltage, so i'm banking on CPU temp being at fault. Plus I still got WHEA errors. I believe If I get a top of the line water cooling system I can get proper scores and less or no errors. Right now I sport a simple H100i, which is good enough for 1.5v LLC1 and not get crazy hot.
Thermal throttling begins at Tctl = 95 C. Using Sense Skew and cooling my 1800X usually doesn't hit that at all. I did a quick run at 4.1 using +0.15 V instead of the +0.05 V I used for 4.0. Score at 4.1 + 3300-CL14 is 1800 - 1817, so my former run used slower RAM settings. Which goes to show that RAM frequency impacts CB scores.

Interestingly CB lists the CPU as 4.0 is Elmor's Zenstate program is used to up the frequency.
Edited by Timur Born - 4/25/17 at 12:09am
post #11359 of 17583
Quote:
Originally Posted by Clukos View Post

This is what my report looks like: https://drive.google.com/open?id=0B4hoXY-91SDFcmxwRGhKN2h4b2c

How can I get the .dbg files by the way? From what I can understand it looks like I lost all XMP info on one stick. Used the Aura software only (not the G.Skill one).

You need to run HWiNFO in Debug Mode, see here for more details about that: https://www.hwinfo.com/forum/Thread-IMPORTANT-Read-this-before-submitting-a-report

I believe the problem with corrupted SPD is due to a conflict between software that writes to SPD and any other software that accesses SPD during the same time.
DDR4 has 2 banks of 256 bytes for SPD and to read the entire SPD, it's required to send a command (via SMBus) to switch the banks.
So if such a bank switch command happens during the write cycle, it can cause corruption.
Another problem might happen if multiple tools send an SMBus command at the same time, not just a bank switch. So such conflict could also be caused by lots of sensor monitoring tools that access SMBus.

To avoid problems of concurrent SPD access, tools like HWiNFO, AIDA64, CPU-Z, SIV and some others are synchronized - we use a global mutex, which we hold during the entire access operation and anyone else attempting to access SPD (if using the same mechanism) will wait for that mutex and only if it's released, will perform the operation.
I believe that Aura or G.Skill software don't support this mechanism and think they're the only ones accessing SPD. Not sure about Typhoon, but I recall we've been asking its author to implemented it (though my last info was that he didn't do it). Anyway, a correct implementation of synchronization would require that ALL tools accessing SPD support this mechanism. This should significantly reduce the probability of a conflict, though you can't avoid that for 100%. Writing to SPD should never be done, it's a fatal design. Several Intel systems block SPD write access as a security mechanism.
Edited by Mumak - 4/25/17 at 12:51am
post #11360 of 17583
Quote:
Originally Posted by Mumak View Post

You need to run HWiNFO in Debug Mode, see here for more details about that: https://www.hwinfo.com/forum/Thread-IMPORTANT-Read-this-before-submitting-a-report.

Thank you, this is what I got after 3 runs: https://drive.google.com/open?id=0B4hoXY-91SDFaEFkNnF2YkQ5Y1E
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