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post #13011 of 17390
Quote:
Originally Posted by hotstocks View Post

That sound stuttering/robo voice happens to me too, and I use Firefox, which grows ram forever and I have to close processes. That said I do have like 20-100 tabs open, so probably my fault. Though I think flash or something in Firefox is using way too much memory when I am not even using the tabs, like it keeps loading stuff forever till crashes or slows down to a halt, but this was happening on my 4 core intel also, so I think it is more to do with ****ty browsers not cleaning up their memory, prefetching the wrong tabs that you are not even open, etc. Hope new version of Firefox fixes this stuff, and yes since browser are gpu acccelerated (though I have turned that off and no help), who knows what is really going on.

I'm sorry that my suggestion to you back at post 10626 didn't help with Firefox.
     
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post #13012 of 17390
I saw the posts regarding latency in regard to SOC while I was at work and wanted to investigate further. As suspected, I saw no differences in cache latencies. With that said, there certainly seemed to be a trend in regard to memory latency at 1.15v.

Edit: all tests were done with identical settings with the exception of SOC. Each run was done 1-2 minutes after a reboot. The lowest my memory runs semi reliably is with SOC @.95v (you can see quite a bit of variation in the results at that voltage). 1.15 has provided the best results with memory stability tests at 3500 for me as well.
Warning: Spoiler! (Click to show)

Edited by madweazl - 5/1/17 at 5:38pm
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post #13013 of 17390
So I took about 8 hours of testing to confirm or discredit a claim made about SOC voltage affecting latency in AIDA64 Cache benchmark.

This was an extremely long and painfully boring process, so I hope this information is appreciated here.

I used the AIDA performance BIAS in my testing to try to give this claim the best possible chance at showing any decreases in latency. So here are my findings.
vSOC - AIDA/GeekBench Bias - Latency Testing (Click to show)
Latency Tests (average of 3 runs):
RAM, L1, L2, L3
0.93750v LLC0
Code 8 OS Load & System Restarts
Not Stable Enough To Test
0.94375v LLC0 0.938v SVI2
68.97, 1, 3.1, 10.1 Code 8 OS Load
0.95000v LLC0 0.944v SVI2
70.67, 1, 3.1, 10.1 Code 8 OS Load
0.95625v LLC0 0.950v SVI2
70.03, 1, 3.1, 10.1 Code 8 OS Load
0.96250v LLC0 0.956v SVI2
70.00, 1, 3.1, 10.1
0.96875v LLC0 0.962v SVI2
69.90, 1, 3.1, 10.1 Code 8 OS Load
0.97500v LLC0 0.969v SVI2
69.97, 1, 3.1, 10.1
0.98125v LLC0 0.975v SVI2
68.53, 1, 3.1, 10.1 Code 8 OS Load
0.98750v LLC0 0.981v SVI2
70.10, 1, 3.1, 10.1
0.99375v LLC0 0.987v SVI2
69.93, 1, 3.1, 10.1
1.00000v LLC0 0.994v SVI2
69.87, 1, 3.1, 10.1
1.00625v LLC0
Code 8, Cannot Load OS
1.01250v LLC0 1.006v SVI2
69.87, 1, 3.1, 10.1 Code 8 OS Load
1.01875v LLC0
Code 8, Cannot Load OS
1.02500v LLC0
Code 8, Cannot Load OS
Notes:
Memory Training Methodology used to get passed code 8 crashes loading OS.
  1. System Code 8 Crashes Loading OS
  2. Force Shutdown
  3. Enter BIOS
  4. 2666 16-16-16-16-36
  5. Save & Exit
  6. 3200 16-16-16-16-36
  7. Save & Exit
  8. 3200 14-14-14-14-34
  9. Save & Exit
  10. Boot Windows
  11. If it still code 8 crashes, go to step 2

On a side note, according to elmor, my CPU has a known bug which is causing its unreliability in booting with any of the BIAS options, so take any failures in my notes with a grain of salt.
I'm only looking at any effects on latency. Unfortunately, this bug has made this testing process painfully long.

My conclusion for the testing is that there is no meaningful difference in latency. To confirm my suspicions that the lowest latency reading I had on memory was just a fluke incident, I loading up that configuration again and tested it again. I re-ran the benchmark several times, sometimes I could get it that low, others not. So it was just a fluke that I got 3 low latencies in a row for the average.

Here is a screenshot after that test. 0.98125v LLC0 0.975v SVI2


So, I would say my results discredit the claims made by a user here that you can tune vSOC to achieve lower L2 and L3 latencies. The only thing that changed, was memory latency, but that was not statistically significant.

That user had submitted "evidence" that was not consistent with any scientific test. They had various CPU clock and reference clock frequencies they had used for examples. When asked for evidence where they used a control for just changes to vSOC, they attacked another user on this forum.

Hope this information helps.

Honorable mentions for @orlfman, @bluej511, and @CeltPC.
Edited by S1L3N7D3A7H - 5/1/17 at 5:52pm
post #13014 of 17390
Quote:
Originally Posted by madweazl View Post

I saw the posts regarding latency in regard to SOC while I was at work and wanted to investigate further. As suspected, I saw no differences in cache latencies. With that said, there certainly seemed to be a trend in regard to memory latency at 1.15v.

Edit: all tests were done with identical settings with the exception of SOC. Each run was done 1-2 minutes after a reboot. The lowest my memory runs semi reliably is with SOC @.95v (you can see quite a bit of variation in the results at that voltage). 1.15 has provided the best results with memory stability tests at 3500 for me as well.
Warning: Spoiler! (Click to show)

Haha, you just did a similar test to mine. I found that the only real way of affecting the L2 and L3 latencies is with changes to memory frequency, core frequency, or reference clock.

I bet if you ran the benchmark a few more times, you would find your lower latency on that 1.15v might have just been a fluke. My lowest latency was on 0.98125v. When I re-tested, I confirmed my suspicions.
post #13015 of 17390
Quote:
Originally Posted by S1L3N7D3A7H View Post

Haha, you just did a similar test to mine. I found that the only real way of affecting the L2 and L3 latencies is with changes to memory frequency, core frequency, or reference clock.

I bet if you ran the benchmark a few more times, you would find your lower latency on that 1.15v might have just been a fluke. My lowest latency was on 0.98125v. When I re-tested, I confirmed my suspicions.

There is a difference between just trying to hit lower latencies, and getting better speeds or getting memory stable at the rated speeds(which is difficult for many of us at the moment).
post #13016 of 17390
Quote:
Originally Posted by S1L3N7D3A7H View Post

So I took about 8 hours of testing to confirm or discredit a claim made about SOC voltage affecting latency in AIDA64 Cache benchmark.

This was an extremely long and painfully boring process, so I hope this information is appreciated here.

I used the AIDA performance BIAS in my testing to try to give this claim the best possible chance at showing any decreases in latency. So here are my findings.
vSOC - AIDA/GeekBench Bias - Latency Testing (Click to show)
Latency Tests (average of 3 runs):
RAM, L1, L2, L3
0.93750v LLC0
Code 8 OS Load & System Restarts
Not Stable Enough To Test
0.94375v LLC0 0.938v SVI2
68.97, 1, 3.1, 10.1 Code 8 OS Load
0.95000v LLC0 0.944v SVI2
70.67, 1, 3.1, 10.1 Code 8 OS Load
0.95625v LLC0 0.950v SVI2
70.03, 1, 3.1, 10.1 Code 8 OS Load
0.96250v LLC0 0.956v SVI2
70.00, 1, 3.1, 10.1
0.96875v LLC0 0.962v SVI2
69.90, 1, 3.1, 10.1 Code 8 OS Load
0.97500v LLC0 0.969v SVI2
69.97, 1, 3.1, 10.1
0.98125v LLC0 0.975v SVI2
68.53, 1, 3.1, 10.1 Code 8 OS Load
0.98750v LLC0 0.981v SVI2
70.10, 1, 3.1, 10.1
0.99375v LLC0 0.987v SVI2
69.93, 1, 3.1, 10.1
1.00000v LLC0 0.994v SVI2
69.87, 1, 3.1, 10.1
1.00625v LLC0
Code 8, Cannot Load OS
1.01250v LLC0 1.006v SVI2
69.87, 1, 3.1, 10.1 Code 8 OS Load
1.01875v LLC0
Code 8, Cannot Load OS
1.02500v LLC0
Code 8, Cannot Load OS
Notes:
Memory Training Methodology used to get passed code 8 crashes loading OS.
  1. System Code 8 Crashes Loading OS
  2. Force Shutdown
  3. Enter BIOS
  4. 2666 16-16-16-16-36
  5. Save & Exit
  6. 3200 16-16-16-16-36
  7. Save & Exit
  8. 3200 14-14-14-14-34
  9. Save & Exit
  10. Boot Windows
  11. If it still code 8 crashes, go to step 2

On a side note, according to elmor, my CPU has a known bug which is causing its unreliability in booting with any of the BIAS options, so take any failures in my notes with a grain of salt.
I'm only looking at any effects on latency. Unfortunately, this bug has made this testing process painfully long.

My conclusion for the testing is that there is no meaningful difference in latency. To confirm my suspicions that the lowest latency reading I had on memory was just a fluke incident, I loading up that configuration again and tested it again. I re-ran the benchmark several times, sometimes I could get it that low, others not. So it was just a fluke that I got 3 low latencies in a row for the average.

Here is a screenshot after that test. 0.98125v LLC0 0.975v SVI2


So, I would say my results discredit the claims made by a user here that you can tune vSOC to achieve lower L2 and L3 latencies. The only thing that changed, was memory latency, but that was not statistically significant.

That user had submitted "evidence" that was not consistent with any scientific test. They had various CPU clock and reference clock frequencies they had used for examples. When asked for evidence where they used a control for just changes to vSOC, they attacked another user on this forum.

Hope this information helps.

Honorable mentions for @orlfman, @bluej511, and @CeltPC.

And this is how you discredit theories, well done. For me soc (surprisingly) didn't even help reaching 3200mhz lol, i can do it with 1.0v just fine, i did notice that cpu core package power goes up with ram speeds (would make sense). And as of right now i am just trying to figure out my cold boot issue, which shockingly might actually have to do with it being cold. I may try to see if it boots successfully in the morning but i still don't get why changing in the BIOS right after a fail would make it work (or maybe its enough for 1min to get the board/cpu/memory at a slightly hotter temp.

Still very confusing though since 2933 has ZERO issues but 3200 does with the strap being the only thing thats changed.
    
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post #13017 of 17390
Quote:
Originally Posted by DDMM1517 View Post

My SPD is damaged, now i can only 2133 at 4x8
I need help!


Yes, that is corrupted for sure. As far as I know your alternatives consist of getting a return or exchange on your modules, or doing a reflash of your SPD's using Thaiphoon Burner. I returned mine, others here have reflashed with excellent results.
post #13018 of 17390
Quote:
Originally Posted by madweazl View Post

I saw the posts regarding latency in regard to SOC while I was at work and wanted to investigate further. As suspected, I saw no differences in cache latencies. With that said, there certainly seemed to be a trend in regard to memory latency at 1.15v.

Edit: all tests were done with identical settings with the exception of SOC. Each run was done 1-2 minutes after a reboot. The lowest my memory runs semi reliably is with SOC @.95v (you can see quite a bit of variation in the results at that voltage). 1.15 has provided the best results with memory stability tests at 3500 for me as well.
Warning: Spoiler! (Click to show)
Quote:
Originally Posted by S1L3N7D3A7H View Post

So I took about 8 hours of testing to confirm or discredit a claim made about SOC voltage affecting latency in AIDA64 Cache benchmark.

This was an extremely long and painfully boring process, so I hope this information is appreciated here.

I used the AIDA performance BIAS in my testing to try to give this claim the best possible chance at showing any decreases in latency. So here are my findings.
vSOC - AIDA/GeekBench Bias - Latency Testing (Click to show)
Latency Tests (average of 3 runs):
RAM, L1, L2, L3
0.93750v LLC0
Code 8 OS Load & System Restarts
Not Stable Enough To Test
0.94375v LLC0 0.938v SVI2
68.97, 1, 3.1, 10.1 Code 8 OS Load
0.95000v LLC0 0.944v SVI2
70.67, 1, 3.1, 10.1 Code 8 OS Load
0.95625v LLC0 0.950v SVI2
70.03, 1, 3.1, 10.1 Code 8 OS Load
0.96250v LLC0 0.956v SVI2
70.00, 1, 3.1, 10.1
0.96875v LLC0 0.962v SVI2
69.90, 1, 3.1, 10.1 Code 8 OS Load
0.97500v LLC0 0.969v SVI2
69.97, 1, 3.1, 10.1
0.98125v LLC0 0.975v SVI2
68.53, 1, 3.1, 10.1 Code 8 OS Load
0.98750v LLC0 0.981v SVI2
70.10, 1, 3.1, 10.1
0.99375v LLC0 0.987v SVI2
69.93, 1, 3.1, 10.1
1.00000v LLC0 0.994v SVI2
69.87, 1, 3.1, 10.1
1.00625v LLC0
Code 8, Cannot Load OS
1.01250v LLC0 1.006v SVI2
69.87, 1, 3.1, 10.1 Code 8 OS Load
1.01875v LLC0
Code 8, Cannot Load OS
1.02500v LLC0
Code 8, Cannot Load OS
Notes:
Memory Training Methodology used to get passed code 8 crashes loading OS.
  1. System Code 8 Crashes Loading OS
  2. Force Shutdown
  3. Enter BIOS
  4. 2666 16-16-16-16-36
  5. Save & Exit
  6. 3200 16-16-16-16-36
  7. Save & Exit
  8. 3200 14-14-14-14-34
  9. Save & Exit
  10. Boot Windows
  11. If it still code 8 crashes, go to step 2

On a side note, according to elmor, my CPU has a known bug which is causing its unreliability in booting with any of the BIAS options, so take any failures in my notes with a grain of salt.
I'm only looking at any effects on latency. Unfortunately, this bug has made this testing process painfully long.

My conclusion for the testing is that there is no meaningful difference in latency. To confirm my suspicions that the lowest latency reading I had on memory was just a fluke incident, I loading up that configuration again and tested it again. I re-ran the benchmark several times, sometimes I could get it that low, others not. So it was just a fluke that I got 3 low latencies in a row for the average.

Here is a screenshot after that test. 0.98125v LLC0 0.975v SVI2


So, I would say my results discredit the claims made by a user here that you can tune vSOC to achieve lower L2 and L3 latencies. The only thing that changed, was memory latency, but that was not statistically significant.

That user had submitted "evidence" that was not consistent with any scientific test. They had various CPU clock and reference clock frequencies they had used for examples. When asked for evidence where they used a control for just changes to vSOC, they attacked another user on this forum.

Hope this information helps.

Honorable mentions for @orlfman, @bluej511, and @CeltPC.

Thanks guys, looks like we all had essentially the same conclusion. Stick a fork in that theory thumb.gif

+rep to both of you for great efforts!
post #13019 of 17390
Quote:
Originally Posted by bluej511 View Post

And this is how you discredit theories, well done. For me soc (surprisingly) didn't even help reaching 3200mhz lol, i can do it with 1.0v just fine, i did notice that cpu core package power goes up with ram speeds (would make sense). And as of right now i am just trying to figure out my cold boot issue, which shockingly might actually have to do with it being cold. I may try to see if it boots successfully in the morning but i still don't get why changing in the BIOS right after a fail would make it work (or maybe its enough for 1min to get the board/cpu/memory at a slightly hotter temp.

Still very confusing though since 2933 has ZERO issues but 3200 does with the strap being the only thing thats changed.

I have had similar experiences with something failing, then changing a setting, then changing it back to get passed a failure.

My memory training procedure would get me passed any code 8's at boot at about a 80% or higher chance. Hopefully the may update fixes my bug with the perf BIAS.
post #13020 of 17390
Quote:
Originally Posted by S1L3N7D3A7H View Post

Haha, you just did a similar test to mine. I found that the only real way of affecting the L2 and L3 latencies is with changes to memory frequency, core frequency, or reference clock.

I bet if you ran the benchmark a few more times, you would find your lower latency on that 1.15v might have just been a fluke. My lowest latency was on 0.98125v. When I re-tested, I confirmed my suspicions.

Certainly possible but I ran it three times (every test followed a reboot so there were no back to back tests performed) and each result was consistently better than the other attempts (outside of what I consider flukes here and there). Since my RAM also has the best stability at 1.15 SOC (extensive HCI testing performed), it isn't a stretch that it actually performs well here (1.156 hasn't helped based on previous attempts at higher clocks or tighter latencies but I didn't run in AIDA tests at that setting).
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