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ROG Crosshair VI overclocking thread - Page 2743

post #27421 of 31208
Quote:
Originally Posted by 1usmus View Post

A few words about CPU & SOC phase noise
Warning: Spoiler! (Click to show)
Extreme CAD_BUS 30 30 40 60


Manual CAD_BUS 30 30 40 60

In the extreme mode, the impulse load causes the power phases to react quickly. This generates noise and interference on the cad_bus.
The higher the memory frequency - the more sensitive the bus to noise.

plus information about NX bit

NX bit enable Warning: Spoiler! (Click to show)
NX bit disable Warning: Spoiler! (Click to show)

system works faster rolleyes.gif
Before people start disabling this feature... Do know what your disabling
https://en.wikipedia.org/wiki/NX_bit
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post #27422 of 31208
Quote:
Originally Posted by 1usmus View Post

Warning: Spoiler! (Click to show)
A few words about CPU & SOC phase noise

Extreme CAD_BUS 30 30 40 60


Manual CAD_BUS 30 30 40 60


In the extreme mode, the impulse load causes the power phases to react quickly. This generates noise and interference on the cad_bus.
The higher the memory frequency - the more sensitive the bus to noise.

plus information about NX bit

NX bit enable Warning: Spoiler! (Click to show)

NX bit disable Warning: Spoiler! (Click to show)

system works faster rolleyes.gif

Just an FYI the DPC Latency Checker hasn't working properly on Windows since 8. Use Latencymon.
Quote:
Originally Posted by lordzed83 View Post

I check topic and still cant bealive people are wasting time with dual rank hynix/micron ddr4 kits on ryzen. Save 20 quid then come here whining cant get rated speed.... Its common knowlege now that You buy specific ram for ryzen...

Some people like me bought it months before Ryzen came out and nobody knew anything about how DDR4 would work (or not work) on the platform.

Besides DDR4 is incredibly overpriced right now and if you want a 32GB kit of DR B-Die or a quad channel kit of SR you're basically spending the equivalent of a good custom loop or new CPU.
Edited by chakku - 9/25/17 at 4:07pm
post #27423 of 31208
Quote:
Originally Posted by Miiksu View Post

CB15 1902/173 points. CPU 4.1 GHz. Aida memory 57.7 ns. L1 1 ns, L2 2.9 ns and L3 9.8 ns. Over 34K points in sky diver combined test. GPU clocks only @1148/500. Passmark phycis ~1300 points and 2000 points in single thread test (HPET enabled). If the performance went down then I adjusted sub timings one line at time. So probably I need to do more adjusting again because new CPU and greater overclock.



Quote:
Originally Posted by RS87 View Post

If you post a couple of screenshots for verification you might be able to get your antagonist to eat a couple of slices of humble pie.... tongue.gif

post #27424 of 31208
Quote:
Originally Posted by kaseki View Post


Disabling opcache tends to suppress the segfaults that some Ryzen CPUs reveal when compiling massive jobs using gcc.

https://community.amd.com/thread/215773?start=1620&tstart=0

I disabled opcache for a test and haven't changed it back. Disabling caused a few-percent reduction in performance of some but not all benchmarks. All this is relevant to Linux and Windows emulated Linux (and some less popular Unix-like OSes). It is believed that there is likely some task that can get regular Windows to segfault also, but I am unclear whether such a test has been demonstrated. In any case, AMD is RMA-ing CPUs that demonstrate the issue (not all do). Most on this forum are unlikely to be victims of this processing error.

Okay thanks! thumb.gif
post #27425 of 31208
Quote:
Originally Posted by RS87 View Post

If you post a couple of screenshots for verification you might be able to get your antagonist to eat a couple of slices of humble pie.... tongue.gif

My CB15 scores on the list https://bbs.io-tech.fi/threads/cinebench-r15-testituloksia-v2-0.11733/

I had a bit higher memory speed in this run. But its still around 34K on combined test.
Sky Diver https://www.3dmark.com/3dm/22117691?

Aida64 memory https://s26.postimg.org/6qmlki4hl/cachemem.png

4.0 GHz
HPET disabled
https://s26.postimg.org/5pmcvdni1/2017-08-09_1.png

4.1 GHz
HPET enabled
https://s26.postimg.org/kqoncn67t/2017-09-26.png
Edited by Miiksu - 9/26/17 at 12:49am
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post #27426 of 31208
Im so happy for you man. Your CPU results are beautiful! thumb.gif

But posting pics about that won't magically make this...
Quote:
Originally Posted by Miiksu View Post

Then that's bit weak score. I know I have good memory modules and good IMC. But u get the idea thumb.gif


Any better.

Neither is it evidence of such timings being stable through a full run of HCI Memtest or even AIDA64 memory stress test for a few hours...


Actually, what you just did would the be equal to me saying you have a bad haircut and then, you posting some headless nude pics online.biggrin.gif


tRC: Row cycle time, or the number of clock cycles required for a memory row to complete a full operational cycle. Lower values can notably improve performance, but should not be set lower than tRP+tRAS for stability reasons.

tFAW: Four activation window, or the time that must elapse before new memory banks can be activated after four ACTIVATE commands have been issued. Configured to a minumum 4x tRRD_S, but values >8x tRRD_S are often used for stability.
Quote:
Originally Posted by Blameless View Post

Minimum actual tFAW is tRRD*4. Many boards allow it to be set lower, but it won't actually do anything because tFAW is the minimum time four row activate commands can be sent and tRRD is the row to row delay. You can't issue four row commands in less time than four row activates can be issued, so that's a hard limit.

Most platforms also seem to limit tRRD to 4, but this is not universally the case.
Optimal tRAS is less clear because tRAS is a somewhat flexible window. Absolute minimum that can actually be set appears to be CAS + tRCD, but this is usually too low to actually be usable/stable (and will often be ignored by the platform). A good rule of thumb is CAS + tRCD + tRtP (row to precharge delay, a secondary timing, not tRP). There is usually some wiggle room.

tRRD_S(hort) < tRRD_L(ong) in the same way tWTR_S(hort) < tWTR_L(ong)

tCWL: CAS Write Latency, or the amount of time it takes to write to the open memory bank. WCL is generally configured equal to CAS or CAS-1. This can be a significant timing for stability, and lower values often prove better.

Also, when talking about evidence, we talk about certified stability testing. Not random scores with random bench-runs.

Not to even mention that your are tagged "KR" (KILL RUN, NOT 24/7 STABLE) in the Cinebench results you shared.

But that's fine man, because even then it is irrelevant to the point: the memory timings you were bragging about are still all wrong and over the place.

Nevertheless, please, do show us how good and stable those memory timings are working for you. I bet you that humble pie...




They are not.
post #27427 of 31208
Quote:
Originally Posted by Miiksu View Post

U can cry. It does not matter. My performance is great. Better than most people at same clocks.

LoL dude...

Have you even tested stability on that? xD

It is ALL out of sync...
post #27428 of 31208
Quote:
Originally Posted by lordzed83 View Post

Atm im got Team Group 3733 cl18 but so tempted to swap for this


https://www.overclockers.co.uk/team-group-dark-pro-8pack-edition-16gb-2x8gb-ddr4-pc4-25600c14-3200mhz-dual-channel-kit-black-my-08l-tg.html


To play around tongue.gif

MY GOODNESS! drool.gif

Please report back if you eventually test those.

I wish I could get a pair like that in Argentina!

They even have a ten years warranty! bigeyedsmiley.png
post #27429 of 31208
@Ex0cet
Quote:
Originally Posted by AmxdPt View Post

LoL dude...

Have you even tested stability on that? xD

It is ALL out of sync...
With last cpu it was fully stable. I havent yet tested with this better cpu.
Edited by Miiksu - 9/26/17 at 6:46am
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post #27430 of 31208
With those timmings?
Quote:
Originally Posted by Miiksu View Post

@Ex0cet
Last cpu it was fully stable. I havent yet tested with this better cpu.

With those timmings?

You can't be serious...
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