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post #8691 of 17159
What exactly is "SIO clock skew" supposed to be? Is this the same as "SenseMI clock skew"? And how could a CPU temperature related setting lead to bricking some chip on the mainboard, when the voltage is increased above 1.2v, but not when the setting is disabled? Will the setting combination also influence some shadow voltage value?
post #8692 of 17159
Quote:
Originally Posted by Reikoji View Post

Can the strain on VRM be gauged somewhat with how much VRM temperature is increasing?

The temp change will come from the disparity in applied voltages between different LLC levels. The actual strain on the FETs comes from elevated current demand within a given timeframe. If you match the load voltages, the temp differences (if any) won't be large.
post #8693 of 17159
Quote:
Originally Posted by Raja@ASUS View Post

The temp change will come from the disparity in applied voltages between different LLC levels. The actual strain on the FETs comes from elevated current demand within a given timeframe. If you match the load voltages, the temp differences (if any) won't be large.

What do we use to match the load voltages at home if not SVI2?
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post #8694 of 17159
Quote:
Originally Posted by Timur Born View Post

In the end everyone has to measure this on their own.

Agree, everyone has their own right to choose what they do.
Quote:
Originally Posted by Reikoji View Post

Monitoring software cant poll fast enough

Agree, I reckon all we know is where we are in a "ballpark area".
Quote:
Originally Posted by Raja@ASUS View Post

This is where elementary understanding of LLC helps. You just need to set the correct VID to get the required load voltage. Nothing else to it, really.

Thank you, this is what The Stilt advised as well to members.
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post #8695 of 17159
My elementary understanding of LLC.

Edit: will have to try and create some 50-75% loads when I get home to see how the different LLC levels react.
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post #8696 of 17159
Quote:
Originally Posted by Raja@ASUS View Post

The temp change will come from the disparity in applied voltages between different LLC levels. The actual strain on the FETs comes from elevated current demand within a given timeframe. If you match the load voltages, the temp differences (if any) won't be large.
Of course the high quality VRM section of the CH6 can deal with a little strain, can it not?! That's why we bought this flagship mainboard. tongue.gif
post #8697 of 17159
Quote:
Originally Posted by madweazl View Post

What do we use to match the load voltages at home if not SVI2?

If you have no measuring equipment at all, when changing to a lower LLC level, simply keep increasing the set VID in 10mV steps until the system is stable.
post #8698 of 17159
Hi all, on bios 0083 my ram speeds seem to be resetting themselves on reboot. If I go into the bios it always says the target is 3200mhz, if I boot after examining those speeds in the bios my PC will boot fine with 3200mhz cl14 14 14 34, if i just reboot it switches to 2133mhz - unsure of the timings. This is with G.skill 3200C14D 16GVR ram. Any help would be appreciated.
post #8699 of 17159
Quote:
Originally Posted by orlfman View Post

here's a pic with high performance profile selected:

there really doesn't appear to be much of a difference. the averages and lows are pretty much the same. highs are similar. the current was different because the moment i took the snapshot my steam in the background in the system tray started to do an update. it really seems like ryzen balance and high performance are identical... at least in my case with XFR disabled.

Take a picture of the difference between balanced using 5% minimum processor vs. Ryzen balanced and you'll also see almost no difference as well.
Quote:
Originally Posted by Reikoji View Post

They are, because both high performance and ryzen balance keep processors @ whatever Pstate 0 is. 90% isnt going to drop states, or idle power usage any significant level.
There are also various other settings normally hidden that AMD most likely altered to get the 2-4 wat drop between 90% and 100%, and IMO it is not the 90% and 100% that is doing it.

Have you tried changing your ryzen balanced power plan's minimum processor state from 90% to 100% and see what difference that makes in the cpu package power?

The 2-4 watts difference that I'm referring to is not the difference between 90% and 100%. It is the difference between 5% and 90%. As I said above, check out the difference in watts between 5% minimum processor vs. Ryzen balanced at 90%. It is a 2-4 watt difference at idle.

Basically though, what you're saying is that AMD released the power plan, and then decided to talk about the P-States knowing that none of the P-States matter if people are using their own power plan? Also, why such a small difference between using 5% minimum processor and 90% with Ryzen balanced?
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post #8700 of 17159
Quote:
Originally Posted by Raja@ASUS View Post

If you have no measuring equipment at all, when changing to a lower LLC level, simply keep increasing the set VID in 10mV steps until the system is stable.

I have a couple DMMs but measurements taken off the back of the mobo by another user in correlation with elmor and mumak's findings indicate that SVI2 appears to be the most accurate measurement at the CPU right now vs the ProbeIt location. The delta between SVI2 and SIO(?) is significant at LLC5 (about 42mv at max and 36mv average). 42mv is consistent with your o-scope findings at LLC5 IIRC. Again, I appreciate the input.
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