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Preliminary view of AMD VEGA Bios - Page 59

post #581 of 817
Quote:
Originally Posted by Nuke33 View Post

So 1148mhz is my max error free HBM frequency. 1150mhz gives me errors in OCCT. I have not determined a limit for SoC frequency though. 1200mhz works flawlessly.
Yes, for memspeed above 1150mhz it seems to give some "fake" hashrate, meaning that internal compute errors result in less found shares. Miner doesn't report errors ...
post #582 of 817
how many watts for those figures @rednow ?
post #583 of 817
Quote:
Originally Posted by gupsterg View Post

@Nuke33

Many +rep for your shares of testing thumb.gif , thank you biggrin.gif .

May I ask do you have V56? also is your die molded? as hotspot temp would seem to suggest this to me.

Thank you very much. biggrin.gif
But the truth is that you should get those reps instead since you were the one who made it possible in the first place wink.gif


Unfortunately I do not own a V56. My V64 has a molded die and I used Conductonaut on it.
post #584 of 817
Quote:
Originally Posted by rednow View Post

gupsterg and Nuke33 - you are awesome!
Pitty I cannot + REP.

Vega64 liquid 1408/1100 before 1408/1150 after
eth 44.2 before 46.2 after
xmr 1990 before 2150 after
))

"Slow" card on screens is Vega56 running 1408/1100

Thanks smile.gif

Nice scores, thank you for confirming it works! thumb.gif
Quote:
Originally Posted by rednow View Post

Yes, for memspeed above 1150mhz it seems to give some "fake" hashrate, meaning that internal compute errors result in less found shares. Miner doesn't report errors ...

1150mhz works at first for me but as the waterloop heats up it throws a few errors here and there. Not much but I am a fan of stability, so 1148mhz it is smile.gif

I have to say I was actually suprised that it reached that high. From 945mhz to 1148mhz we get an increase of ~22% memory bandwidth. That is insane considering those gains are almost free of powerconsumption increase.
Edited by Nuke33 - 10/23/17 at 11:14am
post #585 of 817
The liquid version have only 5 p-states for SoC ?

In my case (air bios, reg hellm), i have 8 p-states for SoC, or i'm on wrong way...
post #586 of 817
Thread Starter 
@Nuke33

Thanks for info, sweet hotspot temp for sure smile.gif .

@Star2k

You are correct.

I was going to spend time making marked images of each edition PowerPlay to add to OP, I have not found time today.

In the powerplay is header which has pointer to SOCCLK table (blue highlight), 2nd byte denotes number of entries (green line), each entry is clock (4 bytes) and then ID (1 byte/orange line).

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post #587 of 817
Quote:
Originally Posted by rednow View Post

gupsterg and Nuke33 - you are awesome!
Pitty I cannot + REP.

Vega64 liquid 1408/1100 before 1408/1150 after
eth 44.2 before 46.2 after
xmr 1990 before 2150 after

"Slow" card on screens is Vega56 running 1408/1100

What driver are you currently on? What are you using to lock in your core voltage that low?
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post #588 of 817
Ok ! Thanks for explanation.
post #589 of 817
Thread Starter 
@Star2k

No problem smile.gif .

I have been viewing PowerPlay from VBIOS and yesterday did note malformed PowerPlay for RX VEGA 56. VBIOS being studied was one which Buildzoid posted in thread,

VER016.001.001.000.008766
07/30/17 17:26

Header translation
Warning: Spoiler! (Click to show)
Code:
typedef struct _ATOM_Vega10_POWERPLAYTABLE {
        struct atom_common_table_header sHeader;
00                      UCHAR  ucTableRevision;
5C 00                   USHORT usTableSize;                        /* the size of header structure */
EF 06 00 00             ULONG  ulGoldenPPID;                       /* PPGen use only */
0E 2C 00 00             ULONG  ulGoldenRevision;                   /* PPGen use only */
1B 00                   USHORT usFormatID;                         /* PPGen use only */
48 00 00 00             ULONG  ulPlatformCaps;                     /* See ATOM_Vega10_CAPS_* */
80 A9 03 00 (2400MHz)   ULONG  ulMaxODEngineClock;                 /* For Overdrive. */
F0 49 02 00 (1500MHz)   ULONG  ulMaxODMemoryClock;                 /* For Overdrive. */
32 00                   USHORT usPowerControlLimit;
08 00                   USHORT usUlvVoltageOffset;                 /* in mv units */
00 00                   USHORT usUlvSmnclkDid;
00 00                   USHORT usUlvMp1clkDid;
00 00                   USHORT usUlvGfxclkBypass;
00 00                   USHORT usGfxclkSlewRate;
00                      UCHAR  ucGfxVoltageMode;
00                      UCHAR  ucSocVoltageMode;
00                      UCHAR  ucUclkVoltageMode;
00                      UCHAR  ucUvdVoltageMode;
00                      UCHAR  ucVceVoltageMode;
02                      UCHAR  ucMp0VoltageMode;
01                      UCHAR  ucDcefVoltageMode;
5C 00 (0x5Ch)           USHORT usStateArrayOffset;                 /* points to ATOM_Vega10_State_Array */
40 02 (0x240h)          USHORT usFanTableOffset;                   /* points to ATOM_Vega10_Fan_Table */
37 02 (0x237h)          USHORT usThermalControllerOffset;          /* points to ATOM_Vega10_Thermal_Controller */
94 00 (0x94h)           USHORT usSocclkDependencyTableOffset;      /* points to ATOM_Vega10_SOCCLK_Dependency_Table */
8F 01 (0x18Fh)          USHORT usMclkDependencyTableOffset;        /* points to ATOM_Vega10_MCLK_Dependency_Table */
B4 00 (0xB4h)           USHORT usGfxclkDependencyTableOffset;      /* points to ATOM_Vega10_GFXCLK_Dependency_Table */
1E 01 (0x11Eh)          USHORT usDcefclkDependencyTableOffset;     /* points to ATOM_Vega10_DCEFCLK_Dependency_Table */
7A 00 (0x7Ah)           USHORT usVddcLookupTableOffset;            /* points to ATOM_Vega10_Voltage_Lookup_Table */
8C 00 (0x8Ch)           USHORT usVddmemLookupTableOffset;          /* points to ATOM_Vega10_Voltage_Lookup_Table */
AD 01 (0x1ADh)          USHORT usMMDependencyTableOffset;          /* points to ATOM_Vega10_MM_Dependency_Table */
00 00                   USHORT usVCEStateTableOffset;              /* points to ATOM_Vega10_VCE_State_Table */
00 00                   USHORT usReserve;                          /* No PPM Support for Vega10 */
63 02 (0x263h)          USHORT usPowerTuneTableOffset;             /* points to ATOM_Vega10_PowerTune_Table */
00 00                   USHORT usHardLimitTableOffset;             /* points to ATOM_Vega10_Hard_Limit_Table */
90 00 (0x90h)           USHORT usVddciLookupTableOffset;           /* points to ATOM_Vega10_Voltage_Lookup_Table */
99 02 (0x299h)          USHORT usPCIETableOffset;                  /* points to ATOM_Vega10_PCIE_Table */
5E 01 (0x15Eh)          USHORT usPixclkDependencyTableOffset;      /* points to ATOM_Vega10_PIXCLK_Dependency_Table */
34 01 (0x134h)          USHORT usDispClkDependencyTableOffset;     /* points to ATOM_Vega10_DISPCLK_Dependency_Table */
88 01 (0x188h)          USHORT usPhyClkDependencyTableOffset;      /* points to ATOM_Vega10_PHYCLK_Dependency_Table */
} ATOM_Vega10_POWERPLAYTABLE;

SOCCLK translation
Warning: Spoiler! (Click to show)
Code:
typedef struct _ATOM_Vega10_SOCCLK_Dependency_Table {
00    UCHAR ucRevId;
06    UCHAR ucNumEntries;                                         /* Number of entries. */
    ATOM_Vega10_CLK_Dependency_Record entries[1];            /* Dynamically allocate entries. */
} ATOM_Vega10_SOCCLK_Dependency_Table;

typedef struct _ATOM_Vega10_CLK_Dependency_Record {
60 EA 00 00 (600MHz)    ULONG  ulClk;                                               /* Frequency of Clock */
00                      UCHAR  ucVddInd;                                            /* Base voltage */
} ATOM_Vega10_CLK_Dependency_Record;

typedef struct _ATOM_Vega10_CLK_Dependency_Record {
40 19 01 00 (720MHz)    ULONG  ulClk;                                               /* Frequency of Clock */
01                      UCHAR  ucVddInd;                                            /* Base voltage */
} ATOM_Vega10_CLK_Dependency_Record;

typedef struct _ATOM_Vega10_CLK_Dependency_Record {
DC 4A 01 00 (847MHz)    ULONG  ulClk;                                               /* Frequency of Clock */
02                      UCHAR  ucVddInd;                                            /* Base voltage */
} ATOM_Vega10_CLK_Dependency_Record;

typedef struct _ATOM_Vega10_CLK_Dependency_Record {
00 77 01 00 (960MHz)    ULONG  ulClk;                                               /* Frequency of Clock */
03              UCHAR  ucVddInd;                                            /* Base voltage */
} ATOM_Vega10_CLK_Dependency_Record;

typedef struct _ATOM_Vega10_CLK_Dependency_Record {
        ULONG  ulClk;                                               /* Frequency of Clock */
        UCHAR  ucVddInd;                                            /* Base voltage */
} ATOM_Vega10_CLK_Dependency_Record;

typedef struct _ATOM_Vega10_CLK_Dependency_Record {
90 91 01 00 (1028MHz)   ULONG  ulClk;                                               /* Frequency of Clock */
05                      UCHAR  ucVddInd;                                            /* Base voltage */
} ATOM_Vega10_CLK_Dependency_Record;

typedef struct _ATOM_Vega10_CLK_Dependency_Record {
        ULONG  ulClk;                                               /* Frequency of Clock */
        UCHAR  ucVddInd;                                            /* Base voltage */
} ATOM_Vega10_CLK_Dependency_Record;

typedef struct _ATOM_Vega10_CLK_Dependency_Record {
6C B0 01 00 (1107MHz)   ULONG  ulClk;                                               /* Frequency of Clock */
07                      UCHAR  ucVddInd;                                            /* Base voltage */
} ATOM_Vega10_CLK_Dependency_Record;


The table occupies the correct space, does not have 6 entries, then ucVddInd is not consecutively increasing. Really strange to say the least.

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post #590 of 817
Quote:
Originally Posted by gupsterg View Post


I have been viewing PowerPlay from VBIOS and yesterday did note malformed PowerPlay for RX VEGA 56. VBIOS being studied was one which Buildzoid posted in thread,

VER016.001.001.000.008766
07/30/17 17:26

Header translation
Warning: Spoiler! (Click to show)
Code:
typedef struct _ATOM_Vega10_POWERPLAYTABLE {
        struct atom_common_table_header sHeader;
00                      UCHAR  ucTableRevision;
5C 00                   USHORT usTableSize;                        /* the size of header structure */
EF 06 00 00             ULONG  ulGoldenPPID;                       /* PPGen use only */
0E 2C 00 00             ULONG  ulGoldenRevision;                   /* PPGen use only */
1B 00                   USHORT usFormatID;                         /* PPGen use only */
48 00 00 00             ULONG  ulPlatformCaps;                     /* See ATOM_Vega10_CAPS_* */
80 A9 03 00 (2400MHz)   ULONG  ulMaxODEngineClock;                 /* For Overdrive. */
F0 49 02 00 (1500MHz)   ULONG  ulMaxODMemoryClock;                 /* For Overdrive. */
32 00                   USHORT usPowerControlLimit;
08 00                   USHORT usUlvVoltageOffset;                 /* in mv units */
00 00                   USHORT usUlvSmnclkDid;
00 00                   USHORT usUlvMp1clkDid;
00 00                   USHORT usUlvGfxclkBypass;
00 00                   USHORT usGfxclkSlewRate;
00                      UCHAR  ucGfxVoltageMode;
00                      UCHAR  ucSocVoltageMode;
00                      UCHAR  ucUclkVoltageMode;
00                      UCHAR  ucUvdVoltageMode;
00                      UCHAR  ucVceVoltageMode;
02                      UCHAR  ucMp0VoltageMode;
01                      UCHAR  ucDcefVoltageMode;
5C 00 (0x5Ch)           USHORT usStateArrayOffset;                 /* points to ATOM_Vega10_State_Array */
40 02 (0x240h)          USHORT usFanTableOffset;                   /* points to ATOM_Vega10_Fan_Table */
37 02 (0x237h)          USHORT usThermalControllerOffset;          /* points to ATOM_Vega10_Thermal_Controller */
94 00 (0x94h)           USHORT usSocclkDependencyTableOffset;      /* points to ATOM_Vega10_SOCCLK_Dependency_Table */
8F 01 (0x18Fh)          USHORT usMclkDependencyTableOffset;        /* points to ATOM_Vega10_MCLK_Dependency_Table */
B4 00 (0xB4h)           USHORT usGfxclkDependencyTableOffset;      /* points to ATOM_Vega10_GFXCLK_Dependency_Table */
1E 01 (0x11Eh)          USHORT usDcefclkDependencyTableOffset;     /* points to ATOM_Vega10_DCEFCLK_Dependency_Table */
7A 00 (0x7Ah)           USHORT usVddcLookupTableOffset;            /* points to ATOM_Vega10_Voltage_Lookup_Table */
8C 00 (0x8Ch)           USHORT usVddmemLookupTableOffset;          /* points to ATOM_Vega10_Voltage_Lookup_Table */
AD 01 (0x1ADh)          USHORT usMMDependencyTableOffset;          /* points to ATOM_Vega10_MM_Dependency_Table */
00 00                   USHORT usVCEStateTableOffset;              /* points to ATOM_Vega10_VCE_State_Table */
00 00                   USHORT usReserve;                          /* No PPM Support for Vega10 */
63 02 (0x263h)          USHORT usPowerTuneTableOffset;             /* points to ATOM_Vega10_PowerTune_Table */
00 00                   USHORT usHardLimitTableOffset;             /* points to ATOM_Vega10_Hard_Limit_Table */
90 00 (0x90h)           USHORT usVddciLookupTableOffset;           /* points to ATOM_Vega10_Voltage_Lookup_Table */
99 02 (0x299h)          USHORT usPCIETableOffset;                  /* points to ATOM_Vega10_PCIE_Table */
5E 01 (0x15Eh)          USHORT usPixclkDependencyTableOffset;      /* points to ATOM_Vega10_PIXCLK_Dependency_Table */
34 01 (0x134h)          USHORT usDispClkDependencyTableOffset;     /* points to ATOM_Vega10_DISPCLK_Dependency_Table */
88 01 (0x188h)          USHORT usPhyClkDependencyTableOffset;      /* points to ATOM_Vega10_PHYCLK_Dependency_Table */
} ATOM_Vega10_POWERPLAYTABLE;

SOCCLK translation
Warning: Spoiler! (Click to show)
Code:
typedef struct _ATOM_Vega10_SOCCLK_Dependency_Table {
00    UCHAR ucRevId;
06    UCHAR ucNumEntries;                                         /* Number of entries. */
    ATOM_Vega10_CLK_Dependency_Record entries[1];            /* Dynamically allocate entries. */
} ATOM_Vega10_SOCCLK_Dependency_Table;

typedef struct _ATOM_Vega10_CLK_Dependency_Record {
60 EA 00 00 (600MHz)    ULONG  ulClk;                                               /* Frequency of Clock */
00                      UCHAR  ucVddInd;                                            /* Base voltage */
} ATOM_Vega10_CLK_Dependency_Record;

typedef struct _ATOM_Vega10_CLK_Dependency_Record {
40 19 01 00 (720MHz)    ULONG  ulClk;                                               /* Frequency of Clock */
01                      UCHAR  ucVddInd;                                            /* Base voltage */
} ATOM_Vega10_CLK_Dependency_Record;

typedef struct _ATOM_Vega10_CLK_Dependency_Record {
DC 4A 01 00 (847MHz)    ULONG  ulClk;                                               /* Frequency of Clock */
02                      UCHAR  ucVddInd;                                            /* Base voltage */
} ATOM_Vega10_CLK_Dependency_Record;

typedef struct _ATOM_Vega10_CLK_Dependency_Record {
00 77 01 00 (960MHz)    ULONG  ulClk;                                               /* Frequency of Clock */
03              UCHAR  ucVddInd;                                            /* Base voltage */
} ATOM_Vega10_CLK_Dependency_Record;

typedef struct _ATOM_Vega10_CLK_Dependency_Record {
        ULONG  ulClk;                                               /* Frequency of Clock */
        UCHAR  ucVddInd;                                            /* Base voltage */
} ATOM_Vega10_CLK_Dependency_Record;

typedef struct _ATOM_Vega10_CLK_Dependency_Record {
90 91 01 00 (1028MHz)   ULONG  ulClk;                                               /* Frequency of Clock */
05                      UCHAR  ucVddInd;                                            /* Base voltage */
} ATOM_Vega10_CLK_Dependency_Record;

typedef struct _ATOM_Vega10_CLK_Dependency_Record {
        ULONG  ulClk;                                               /* Frequency of Clock */
        UCHAR  ucVddInd;                                            /* Base voltage */
} ATOM_Vega10_CLK_Dependency_Record;

typedef struct _ATOM_Vega10_CLK_Dependency_Record {
6C B0 01 00 (1107MHz)   ULONG  ulClk;                                               /* Frequency of Clock */
07                      UCHAR  ucVddInd;                                            /* Base voltage */
} ATOM_Vega10_CLK_Dependency_Record;


The table occupies the correct space, does not have 6 entries, then ucVddInd is not consecutively increasing. Really strange to say the least.

Looks like some kind of dummy/placeholder-mask. Maybe someone just copy and pasted in the sourcecode and forgot to remove that entry.
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