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Preliminary view of AMD VEGA Bios - Page 82

post #811 of 1002
Thread Starter 
OP updated, added:-

https://en.wikipedia.org/wiki/Endianness

https://docs.mql4.com/basis/types/integer/integertypes

https://en.wikipedia.org/wiki/Byte

in useful links smile.gif .
Edited by gupsterg - 11/16/17 at 11:54pm
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post #812 of 1002

could you provide some explanation between the different bios' listed on the front page?
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post #813 of 1002
Thread Starter 
In general and for most of us what each VBIOS has can easily be seen on TPU DB.

So far each reference models VBIOS regardless of version number has same clocks, temperature, powerlimit, etc. Caveat being the difference of PowerLimit between low/high power VBIOS.

The V56 has been artificially gimped "out of the box", with lowest PL and HBM voltage out of all VEGA cards. I don't currently hold the view that HBM differs wildly between V56/V64.
Quote:
AtomBios info

Atom is basically a byte code scripting language used to write little scripts to handle basic card initialization tasks (asic init, setting engine/memory clocks, modesetting).

There are two sets of tables in ATOM: command tables (basically scripts that execute certain functionality) and data tables (structs that store board/system specific information (type and number of connectors/encoders used on the board, power states, ddc lines, panel info, etc.).

The command tables are versioned and there are specific structs defined for the inputs to the command tables. These are all defined in atombios.h and ObjectID.h. Command tables can also call other command tables and look up data in data tables.

Extract from link.

In the past as bios mod was open on other AMD GPUs and ones I meddled heavily with, command tables rarely differed, data tables did. The data tables differed for clocks, etc. Structure was pretty much the same.

The UEFI/GOP module again was same, when a version changed, AFAIK it was to add support for a newer GPU. As UEFI/GOP is backward compatible you could use a newer UEFI/GOP module with a past GPU. For example I used a UEFI/GOP version which came out with Polaris on Fury X.

In the past and even with VEGA, I'm flashing a newer version VBIOS hoping it may fix a bug, etc. Generally for OC'ing on Hawaii/Fiji (and even VEGA) I'm not finding a differing VBIOS improves what the silicon can do. Caveat being I'm using like clocks, PL, etc, etc.

All VBIOS mod allowed me to do on Hawaii/Fiji is set card as I wanted, so I didn't need OS SW to do it. Some aspects OS SW couldn't touch, so again VBIOS mod was better route.
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post #814 of 1002
Thread Starter 
I got undervolt active in lower than DPM5/6/7 biggrin.gif .



DPM_UV.zip 21k .zip file

WattMan gives no access to this.

Last time I try OverdriveNTool I did not work.

This was with PP mod. Gotta now suss the 800MHz HBM lock.

Warning to VEGA FE owners GFX clocks section in Vega64SoftPowerTableEditor is not correct, only do PP mod reg edit by hand.

*** edit ***

OK not got the HBM 800MHz bug when GPU enter higher DPM, just did SP 4K run.

So UV of DPM 1/2/3, so clock range idle to 1138MHz is working via PP mod.
Edited by gupsterg - 11/17/17 at 5:34pm
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post #815 of 1002
Thread Starter 
@subscribers

OP updated smile.gif .

i) Useful links section has AMD VEGA Whitepaper link added.

ii) New section created Testing of PowerPlay registry mods, it has 5 sections which cover testing and observations so far.
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post #816 of 1002

That was quick ^^

 

Thank you, time to start reading :)

    
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post #817 of 1002
Thread Starter 
NP smile.gif , I look forward to comments from readers and discussion plus their testing and observations smile.gif .

Last night I did view PowerPlay again, I could not find what is shown in OverdriveNTool as mV for HBM MEMCLK. In the past, "off the cuff" testing showed adjusting those created issues. I believe it is anomaly within app and needs update to support VEGA better.

Also when browsing VEGA FE PowerPlay it's make up is differing for GfxclkDependencyTable vs RX VEGA, it does not seem to have ACG field.
Code:
typedef struct _ATOM_Vega10_GFXCLK_Dependency_Record {
        ULONG  ulClk;                                               /* Clock Frequency */
        UCHAR  ucVddInd;                                            /* SOC_VDD index */
        USHORT usCKSVOffsetandDisable;                              /* Bits 0~30: Voltage offset for CKS, Bit 31: Disable/enable for the GFXCLK level. */
        USHORT usAVFSOffset;                                        /* AVFS Voltage offset */
} ATOM_Vega10_GFXCLK_Dependency_Record;

typedef struct _ATOM_Vega10_GFXCLK_Dependency_Record_V2 {
        ULONG  ulClk;
        UCHAR  ucVddInd;
        USHORT usCKSVOffsetandDisable;
        USHORT usAVFSOffset;
        UCHAR  ucACGEnable;
        UCHAR  ucReserved[3];
} ATOM_Vega10_GFXCLK_Dependency_Record_V2;

V2 is used by RX VEGA and other is VEGA FE. Perhaps VEGA FE owners can run some tests, provide MSI AB HML files, so we can see how it behaves. This difference is also why @halsafar PowerPlay editing app has an issue with VEGA FE PP editing.

As said before I am no programmer. Just a PC enthusiast dabbling with my HW, hoping to provoke further data/discussions for us to move forward together grouphug.gif .

So far my tweaked OC profile via PP MOD is sweet in further benching and normal usage smile.gif.
Warning: Spoiler! (Click to show)





Edited by gupsterg - 11/18/17 at 2:28pm
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post #818 of 1002
From the Linux Drivers:
Code:
+#define ATOM_Vega10_VoltageMode_AVFS_Interpolate     0
+#define ATOM_Vega10_VoltageMode_AVFS_WorstCase       1
+#define ATOM_Vega10_VoltageMode_Static               2



Has anyone tried a changed Value for the LLR?
Code:
LoadLineResistance; /* in mOhms */

Ok, tried around a bit.... AvP Benchmark Vega56@UV PT +100
at stock 64:
Benchmark Summary:

Number of frames: 25414
Average Frame Time: 4.1ms
Average FPS: 242.2

@96
Benchmark Summary:

Number of frames: 25570
Average Frame Time: 4.1ms
Average FPS: 243.7

@128
Benchmark Summary:

Number of frames: 25763
Average Frame Time: 4.1ms
Average FPS: 245.5

If i calculate right, my card should have a LLR abut 210mOhm under full load....
Edited by BeetleatWar1977 - 11/19/17 at 12:03pm
post #819 of 1002
Thread Starter 
@BeetleatWar1977

+rep for taking the plunge and testing/sharing smile.gif . For me currently not gonna play with LLR, but may in future smile.gif .

@Nuke33

Today was bug fix day biggrin.gif .

I had transferred my usual WattMan profile into reg mod yesterday. This had sorted idle voltage discrepancy from using WattMan. As I used the PC more I started to note that after some time the HBM was stuck at 500MHz and idle voltage 900mV. GPU clocks were though at <50MHz.

I first uninstalled driver and reinstalled, then added PP mod profile. Thinking I caused an issue with them from ACG disable I had been trying to gain last night. As soon as I was on my tweaked profile (using PP mod), after sometime I would have idle issue. So I thought something about PP mod is not emulating stock, as I do not get this issue at stock.

Whilst I fully marked/translated PowerPlay of VBIOS I use and I ran various tests. These tests all failed in resolving idle issue frown.gif . After I completed all marking I had an idea why the issue was happening biggrin.gif . And I have cracked it now biggrin.gif .

My last failed attempt out of many today as example of issue below.

Mid testing.



End testing as fail.




Let's start at the top biggrin.gif .

In PP is State array table. You'll note in the 2nd entry we have SocClockIndexHigh as 05. (Click to show)
Code:
typedef struct _ATOM_Vega10_State_Array {
02      UCHAR ucRevId;
02      UCHAR ucNumEntries;                                         /* Number of entries. */
        ATOM_Vega10_State states[1];                             /* Dynamically allocate entries. */
} ATOM_Vega10_State_Array;

typedef struct _ATOM_Vega10_State {
00              UCHAR  ucSocClockIndexHigh;
00              UCHAR  ucSocClockIndexLow;
00              UCHAR  ucGfxClockIndexHigh;
00              UCHAR  ucGfxClockIndexLow;
00              UCHAR  ucMemClockIndexHigh;
00              UCHAR  ucMemClockIndexLow;
08 00           USHORT usClassification;
00 00 00 00     ULONG  ulCapsAndSettings;
00 00           USHORT usClassification2;
} ATOM_Vega10_State;

typedef struct _ATOM_Vega10_State {
05              UCHAR  ucSocClockIndexHigh;
00              UCHAR  ucSocClockIndexLow;
07              UCHAR  ucGfxClockIndexHigh;
00              UCHAR  ucGfxClockIndexLow;
03              UCHAR  ucMemClockIndexHigh;
00              UCHAR  ucMemClockIndexLow;
05 00           USHORT usClassification;
00 00 00 00     ULONG  ulCapsAndSettings;
00 00           USHORT usClassification2;
} ATOM_Vega10_State;

In SOC table we see 05 is 960MHz. (Click to show)
Code:
typedef struct _ATOM_Vega10_SOCCLK_Dependency_Table {
00    UCHAR ucRevId;
08    UCHAR ucNumEntries;                                         /* Number of entries. */
    ATOM_Vega10_CLK_Dependency_Record entries[1];            /* Dynamically allocate entries. */
} ATOM_Vega10_SOCCLK_Dependency_Table;

typedef struct _ATOM_Vega10_CLK_Dependency_Record {
60 EA 00 00 (600MHz)    ULONG  ulClk;                                               /* Frequency of Clock */
00                      UCHAR  ucVddInd;                                            /* Base voltage */

} ATOM_Vega10_CLK_Dependency_Record;
typedef struct _ATOM_Vega10_CLK_Dependency_Record {
40 19 01 00 (720MHz)    ULONG  ulClk;                                               /* Frequency of Clock */
01                      UCHAR  ucVddInd;                                            /* Base voltage */

} ATOM_Vega10_CLK_Dependency_Record;
typedef struct _ATOM_Vega10_CLK_Dependency_Record {
80 38 01 00  (800MHz)   ULONG  ulClk;                                               /* Frequency of Clock */
02                      UCHAR  ucVddInd;                                            /* Base voltage */

} ATOM_Vega10_CLK_Dependency_Record;
typedef struct _ATOM_Vega10_CLK_Dependency_Record {
DC 4A 01 00  (847MHz)   ULONG  ulClk;                                               /* Frequency of Clock */
03                      UCHAR  ucVddInd;                                            /* Base voltage */

} ATOM_Vega10_CLK_Dependency_Record;
typedef struct _ATOM_Vega10_CLK_Dependency_Record {
90 5F 01 00  (900MHz)   ULONG  ulClk;                                               /* Frequency of Clock */
04                      UCHAR  ucVddInd;                                            /* Base voltage */

} ATOM_Vega10_CLK_Dependency_Record;
typedef struct _ATOM_Vega10_CLK_Dependency_Record {
00 77 01 00 (960MHz)    ULONG  ulClk;                                               /* Frequency of Clock */
05                      UCHAR  ucVddInd;                                            /* Base voltage */

} ATOM_Vega10_CLK_Dependency_Record;
typedef struct _ATOM_Vega10_CLK_Dependency_Record {
90 91 01 00 (1028MHz)   ULONG  ulClk;                                               /* Frequency of Clock */
06                      UCHAR  ucVddInd;                                            /* Base voltage */

} ATOM_Vega10_CLK_Dependency_Record;
typedef struct _ATOM_Vega10_CLK_Dependency_Record {
6C B0 01 00 (1107MHz)   ULONG  ulClk;                                               /* Frequency of Clock */
07                      UCHAR  ucVddInd;                                            /* Base voltage */
} ATOM_Vega10_CLK_Dependency_Record;

MCLK DPM 3 is associated with SOC DPM 5 (Click to show)
Code:
typedef struct _ATOM_Vega10_MCLK_Dependency_Table {
01    UCHAR ucRevId;
04    UCHAR ucNumEntries;                                         /* Number of entries. */
    ATOM_Vega10_MCLK_Dependency_Record entries[1];            /* Dynamically allocate entries. */
} ATOM_Vega10_MCLK_Dependency_Table;

typedef struct _ATOM_Vega10_MCLK_Dependency_Record {
3C 41 00 00 (167MHz)    ULONG  ulMemClk;                                            /* Clock Frequency */
00                      UCHAR  ucVddInd;                                            /* SOC_VDD index */
00                      UCHAR  ucVddMemInd;                                         /* MEM_VDD - only non zero for MCLK record */
00                      UCHAR  ucVddciInd;                                          /* VDDCI   = only non zero for MCLK record */
} ATOM_Vega10_MCLK_Dependency_Record;

typedef struct _ATOM_Vega10_MCLK_Dependency_Record {
50 C3 00 00 (500MHz)    ULONG  ulMemClk;                                            /* Clock Frequency */
00                      UCHAR  ucVddInd;                                            /* SOC_VDD index */
00                      UCHAR  ucVddMemInd;                                         /* MEM_VDD - only non zero for MCLK record */
00                      UCHAR  ucVddciInd;                                          /* VDDCI   = only non zero for MCLK record */
} ATOM_Vega10_MCLK_Dependency_Record;

typedef struct _ATOM_Vega10_MCLK_Dependency_Record {
80 38 01 00 (800MHz)    ULONG  ulMemClk;                                            /* Clock Frequency */
02                      UCHAR  ucVddInd;                                            /* SOC_VDD index */
00                      UCHAR  ucVddMemInd;                                         /* MEM_VDD - only non zero for MCLK record */
00                      UCHAR  ucVddciInd;                                          /* VDDCI   = only non zero for MCLK record */
} ATOM_Vega10_MCLK_Dependency_Record;

typedef struct _ATOM_Vega10_MCLK_Dependency_Record {
24 71 01 00 (945MHz)    ULONG  ulMemClk;                                            /* Clock Frequency */
05                      UCHAR  ucVddInd;                                            /* SOC_VDD index */
00                      UCHAR  ucVddMemInd;                                         /* MEM_VDD - only non zero for MCLK record */
00                      UCHAR  ucVddciInd;                                          /* VDDCI   = only non zero for MCLK record */
} ATOM_Vega10_MCLK_Dependency_Record;

So as I was making HBM DPM 1100MHz and it was associated with SOC DPM 5 (960MHz) this was creating confusion within PowerPlay biggrin.gif .

I have changed:-

i) ucSocClockIndexHigh to 07 of 2nd entry of state array.
ii) SOC DPM 07 to 1199MHz.
iii) MCLK DPM 3 to 1100MHz, but associated with SOC DPM 07.

Pass.



And all is still working biggrin.gifdrum.gif.



Will add this info in OP tomorrow or so smile.gif .
Edited by gupsterg - 11/20/17 at 1:30am
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post #820 of 1002
Good stuff thumb.gif

PP_PhmSoftWTTable in the registry looks interesting, but seems it regenerates itself if modified. I tried to change 167 HBM2 idle to 177


Edited by ducegt - 11/19/17 at 6:37pm
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