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[PCG/Hexus] DDR5 memory is twice as fast as DDR4 and slated for 2019 - Page 13

post #121 of 155
Again, all DRAM is made at multiple densities. I see 4 different densities for DDR3 from 1Gb to 8Gb.

DDR 4GB with 8 chips
https://www.newegg.com/Product/Product.aspx?Item=N82E16820148856
post #122 of 155
I think people missed the point I was making.
post #123 of 155
Quote:
Originally Posted by The Robot View Post

Rambus? I thought they were bankrupt. Glad to hear they pushing innovation instead of parent trolling.

If you ever bothered to read the court Documents you would understand they were the underdog that got screwed over my all the major memory manufactures that teamed up and conspired against them, which is against the law and was proven to have taken place in Court with hard concrete evidence. It's ok though most people are going off what they read back when all this first started which was based on conjecture and a lack of vital information that only came out later in a court of law.

You can thank Rambus for almost every consumer device in the last 15 years that utilizes huge parts of there IP. The Conglomerate Memory manufactures was scared s**tless that a small startup company had developed key critical IP that would shape the foundation of memory for the long foreseeable future and didn't want to be held at the mercy of having to pay royalties to them.

Rambus vs The Big conglomerates was one of if not the biggest DOJ court cases that ever took place but was also plagued by the initial judge who proved to be seriously ignorant when it came to technologically related IP matters or some even alleged a corrupted judge.

Seriously studying up on this case in depth I found it to be very interesting and was quite in eye opener for me.
Edited by Nightingale - 9/28/17 at 12:52pm
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post #124 of 155
Quote:
Originally Posted by darksideleader View Post

Hey its RAMBUS, when do we start sharpening our pitchforks?

After you are done going after all the other Memory manufactures first who initially created the problem that you heavily blame Rambus for.

Rambus is like a person who get's the FRONT PAGE news for being a child rapist. Only after a lengthy court battle is the defendant (Rambus) found innocent and a retraction is legally forced upon those news papers. Only problem is the retraction is printed in the 20th page which most will never see or hear of, thus said person will always be deemed by the general public as still being the child rapist, contrary to the hard evidence documented in court demonstrating otherwise.
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post #125 of 155
Quote:
Originally Posted by grss1982 View Post

Rambus?


With the stunt they and Intel pulled with RDRAM before I'm not really comfortable with what they have planned with DDR5. :|
Quote:
Originally Posted by grss1982 View Post

Rambus?


With the stunt they and Intel pulled with RDRAM before I'm not really comfortable with what they have planned with DDR5. :|

They didn't pull any stunts when you take into context what really took place which sadly most will never know since all they remember was the lies propagated by the big ram Manufactures. There actions were a direct result of the huge unethical and illegal battle they were facing against Billion Dollar companies. Why else would the courts convict them SAMSUNG, Micron and I think Hynix of conspiring, price fixing and sabotage against RAMBUS. Without actually knowing the real story that only came out over 6 years after RAMBUS disappeared, you will never be able to give an objective opinion on the matter.

Why would Intel risk going with Rambus a company that has ZERO experience with fabricating Memory when they could have just more easily went along with the big players that actually produce the stuff. Intel was well aware that RAMBUS legally owned the IP/patents that they filled and created that the competitors chose to steal/utilize in there DDR2 ram without permission.

Fact is if our court systems were 100% pure and uncorrupted then SAMSUNG, MICRON and HYNIX would not exist today. Actually SAMSUNG still would since they have billions invested in other industries. In these type of legal matters if these were smaller companies they would have been fined an amount that they simply would not be able to afford thus bankuptcy would be the end result.

It seems Micron was given some leniency with it being a US company, none the less I am sure someone will write a book about this crazy mess that took place as it's a very complicated case.
Edited by Nightingale - 9/28/17 at 1:24pm
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post #126 of 155
Quote:
Originally Posted by epic1337 View Post

i found this while looking up 16GB sticks.




so yeah, they were indeed 8GB per side, using 1GB per IC package.

Yup, this shows perfectly how SODIMMs are a better choice as I mentioned earlier. Since ECC is so segmented, as well as Registered/Buffered, we don't even use all the pins on a full DIMMs. some are dummy and many unused (since those ICs aren't there).. This is a good image showing that we can get density and a slot reduction at the same time for consumer boards. It would be a gain on space without any loss in functionality.

Just sucks that (probably) none of us are connected to the industry to actual influence some changes. For example, a lot of people really want mini-DTX to happen and we have a really big thread on it. But so far, not much traction. mad.gif


mini-DTX example render by user Aibohphobia. Now imagine this with a slot reduction for SO-DIMMs instead. They could easily add more SATA ports or even a U.2 port there, or other things.



Quote:
Originally Posted by mmonnin View Post

There can be more than 8 chips per side. They even used to be double stacked.

Yeah as Blameless mentioned, this is only with ECC + Registered/Buffered kits. If this was what we got for all consumer kit because it wasn't so artificially segmented, I'd have no issue because they really do maximize the space then. But alas, it doesn't happen for us. We mainly get empty PCB, with dummy and unused pins taking up more space than even an x16 PCIe slot.



  • A PCIe 3.0 x16 slot has 82 pins. Think about how many things we can put in there, even quad NVMe SSDs / NVMe Optane sticks.
  • DDR4 consumer full DIMM has 288 pins.
  • DDR4 SO-DIMMs have 260 pins.

Something just seems so off about this, especially as mentioned, we don't even get easy access to ECC & Buffered ICs. So, we're wasting board space, wasting PCB space and getting nothing in return for it on consumer boards (from gaming, to enthusiast to even workstations who don't opt for ECC).



Speaking of RAMBUS, they even came out with ODR; Octal Data Rate: Eight bits per clock cycle per lane.. Imagine the performance on that if it would have been improved upon like DDR has! It was used on the PS3. =D

https://en.wikipedia.org/wiki/XDR_DRAM

https://en.wikipedia.org/wiki/XDR2_DRAM



Edited by TheBloodEagle - 9/29/17 at 1:09am
post #127 of 155
Hey guys, sorry to bump an old thread but found some more info on DDR5 that I didn't notice before that helped relieve some of the "critique" I had in mind. Seems it is going to have the same pin count as DDR4 and be able to double the I/O exchange per DIMM.









Quote:
 One major change to maintain the reliability of the DDR 5 memory is to place a 1 bit error correction (ECC) function on the silicon die. Up to the DDR4 memory, the ECC function is installed in the memory controller, and the ECC function was not mounted on the DRAM silicon die. However, in DDR 5 generation, ondi ECC is implemented with knowledge of increase in silicon die area.

So maybe ECC will become more ubiquitous and cheaper and less artifically segmented.
Edited by TheBloodEagle - 11/21/17 at 3:03pm
post #128 of 155

This sounds very interesting, ECC might become the standard, which is great.

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post #129 of 155
Quote:
to maintain the reliability of the DDR 5 memory

Interesting statement. The question that will be interesting to see answered in a few years' time is whether ECC might eventually become a necessity for all usage cases due to the increasingly smaller manufacturing processes meaning more and more errors occurring. On a related note, if I recall correctly Intel got a patent a few years ago to have multi-core CPUs with reserve cores being activated in case one or more of the cores that ship activated go bad.

Maybe it's just a result of inevitable errors occurring here and there at the very high speeds that DDR5 will ship at. Let's hope it's just that.
 
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post #130 of 155

Looks like I might just jump from DDR3 to DDR5, lol.

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