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post #351 of 608
Quote:
Originally Posted by 1usmus View Post

I decided to write a small article explaining why some systems work fine at 3200+ and others do not at all

Influence of СLDO_VDDP on MEMCLK "holes"

CLDO_VDDP is a voltage regulator for the module (physical interface) of encoding and decoding of the transmitted and received data stream. The purpose of coding is to simplify the process of restoring the data stream of the receiver. It determines the signals, signal ratios and time parameters necessary for transferring control information, reading and writing data to DRAM devices. In plain language, CLDO_VDDP is the voltage that regulates the memory access at a certain frequency. "Hole" in turn - the frequency gap on which the memory controller can operate with our RAM.

Consider this simple picture:




It shows 3 identical systems (motherboard + RAM + processor). All 3 systems were overclocked and received the following results:

1) The system was perfectly dispersed to a frequency of 3333 MHz
2) The system was accelerated to 2933
3) The system did not start at all

If all systems are the same, why such results? Let's understand. The bottom line is that each memory controller (IMC) has its own technical characteristics ("voltage" and time) and at the same voltage / frequency it will behave differently, namely it will have different access to memory. Red marked our MEMCLK holes, these are the very hole-mediators through which our memory controller communicates with RAM, and if there is no hole in the frequency range chosen by us - the system does not start or start, but the memory runs with errors. At you I think there was a question as these holes to move and expand - all is very simple, voltage CLDO_VDDP allows to spend the given manipulations. The only difficulty is that these holes can not be mathematically calculated. A vivid example of CLDO_VDDP 866 which is magical for many. The hole of this voltage is in the region of 3300-3500 MHz, but again not for all systems. As shown by our internal tests, not all of it works, I repeat all the IMC are different and require a different voltage CLDO_VDDP to achieve the same frequency.

In view of the fact that the shape of the voltage CLDO_VDDP is wave, the minimum voltage change can drastically change the stability of the system. The voltage step is 1 mv. Borders from 700 to 975.

I also want to publish a list of CLDO_VDDP, which can help stabilize your memory

CLDO_VDDP list (volts) (Click to show)
0.562
0.568
0.573
0.579
0.585
0.590
0.596
0.601
0.607
0.613
0.618
0.624
0.630
0.635
0.641
0.646
0.652
0.658
0.663
0.669
0.675
0.680
0.686
0.691
0.697
0.703
0.708
0.714
0.720
0.725
0.731
0.736
0.742
0.748
0.753
0.759
0.765
0.770
0.776
0.781
0.787
0.793
0.798
0.804
0.810
0.815
0.821
0.826
0.832
0.838
0.843
0.849
0.855
0.860
0.866
0.871
0.877
0.883
0.888
0.894
0.900
0.905
0.911
0.916
0.922
0.928
0.933
0.939
0.945
0.950
0.956
0.961
0.961
0.967
0.973

In the Ryzen DRAM Calculator the recommanded CLDO_VDDP value is 425 mV no matter the type of memory you have. ALT 1 is 866 mV and ALT 2 is 945 mV. Is there an error there? You said earlier "The voltage step is 1 mv. Borders from 700 to 975." 425 mV is way lower than 700.
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post #352 of 608
Thread Starter 
Quote:
Originally Posted by figarro View Post

Any ideas what to do when testing different CLDO_VDDP settings and the system fails memory training? When do I power down the system to cold boot (so that a new voltage is applied)? If I let the system fail testing it gets to the Press F1 screen...

here, unfortunately, you always need a cold start in order to return the desired value
Quote:
Originally Posted by figarro View Post

In the Ryzen DRAM Calculator the recommanded CLDO_VDDP value is 425 mV no matter the type of memory you have. ALT 1 is 866 mV and ALT 2 is 945 mV. Is there an error there? You said earlier "The voltage step is 1 mv. Borders from 700 to 975." 425 mV is way lower than 700.

All the voltages are safe, I will soon release a new version of the calculator with new recommendations.This voltage has a waveform of the signal. That is, after a certain period, the memory loses stability and again gets it. A finer adjustment requires a step-by-step selection of voltage.At the moment I like 425 and 700 very much.
Edited by 1usmus - 11/24/17 at 5:51am
post #353 of 608
Quote:
Originally Posted by figarro View Post

Any ideas what to do when testing different CLDO_VDDP settings and the system fails memory training? When do I power down the system to cold boot (so that a new voltage is applied)? If I let the system fail testing it gets to the Press F1 screen...

What I did when plodding through the CLDO_VDDP/Proc_ODT morass was to let the system try to POST, and after a few F9s I would push the "start" button at the lower edge of the board (in vertical ATX cases). The BIOS would then restart and POST at 2133 (for my 2 x 16 RAM) but leave all the settings in the BIOS alone. I could then try a new CLDO-VDDP and/or Proc_ODT. It was possible this way to map out various areas where the memory hole was or wasn't, while taking only a minute or so for each test.

However, note that to get the setting in the AMD menu section to "take," it is necessary to do a BIOS hard restart, which occurs automatically if one changes the DRAM boot voltage by a tiny amount (suggestion from RAMAD).
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post #354 of 608
Quote:
Originally Posted by 1usmus View Post

try this vboot = vdram , cldo_vddp 0.700, soc 1.05

I understand that the vBoot is only used during the training phase and then the vdram is used post training?

If it is, couldn't extra voltage for the training phase assist in having more consistent memory training/sync?

Is there any methodology behind setting cldo_vddp or is it one of those "i've tested/observed lots and this seems best with frequency X, latency Y, voltage Z"?

I.E. is more CLDO beneficial for higher clocks, or lower clocks? Or is it literally 100% random across all IMCs with some voltages that seem to be 'OK for most'?

When I come to fiddling with 3600 what is your recommendation for SOC, vDRAM/BOOT/CLDO_VDDP and VDDP? I can give it a whirl over the next few days and see what happens as i'll be back at work and can leave memtest running for up to 14 hrs
Edited by blair - 11/24/17 at 8:55am
post #355 of 608

With my little understanding and poor drawing skill i'll try to "explain" how cldo_vddp work.

The curve represente your dram voltage signal, changing cldo_vddp move back and forth this signal compared to your available frequency setting.

The purpose to changing it is to make the curve crossed your setting line on the appropriate frequency setting.

Whereas the zone where there is no curve present is a memory hole .

Depending of your IMC or RAM the curve can vary in lenght or thickness.

If i understand it properly, it work like that.

 

Sorry for my poor english.


Edited by poisson21 - 11/24/17 at 9:45am
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post #356 of 608
Thread Starter 
Quote:
Originally Posted by poisson21 View Post

With my little understanding and poor drawing skill i'll try to "explain" how cldo_vddp work.


The curve represente your dram voltage signal, changing cldo_vddp move back and forth this signal compared to your available frequency setting.
The purpose to changing it is to make the curve crossed your setting line on the appropriate frequency setting.
Whereas the zone where there is no curve present is a memory hole .
Depending of your IMC or RAM the curve can vary in lenght or thickness.
If i understand it properly, it work like that.

Sorry for my poor english.

All is true, only the form is more oblate, in dozens of times

post #357 of 608
This post...

I want to frame it in platinum on my wall because I've struggled with my sk-hynix 3200 set since this systems inception. I can't believe I went from 2933 to 3333 so far with using all of the settings on each tab.
 
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post #358 of 608
Thread Starter 
Quote:
Originally Posted by blair View Post

I understand that the vBoot is only used during the training phase and then the vdram is used post training?

If it is, couldn't extra voltage for the training phase assist in having more consistent memory training/sync?

Is there any methodology behind setting cldo_vddp or is it one of those "i've tested/observed lots and this seems best with frequency X, latency Y, voltage Z"?

I.E. is more CLDO beneficial for higher clocks, or lower clocks? Or is it literally 100% random across all IMCs with some voltages that seem to be 'OK for most'?

When I come to fiddling with 3600 what is your recommendation for SOC, vDRAM/BOOT/CLDO_VDDP and VDDP? I can give it a whirl over the next few days and see what happens as i'll be back at work and can leave memtest running for up to 14 hrs

An overabundance of voltage generates digital and thermal noise, increasing the voltage can both positively and negatively affect on system. To simplify your life put vdram = vboot dram.By my observation vboot also takes part in the work of the system after training.

Сalculate СLDO_VDDP is impossible, it is always different. It is also influenced by procODT. The values that the calculator offers are values that work successfully on most systems. They are found purely in practice.

It is extremely difficult to configure the 3600. It is necessary to regulate constantly additional voltages : VPP , VDDP , PLL and VTT DDR. Increasing the voltage to SOC will not help, and in most cases worsen the situation. The controller is very sensitive to noise.
Edited by 1usmus - 11/24/17 at 10:28am
post #359 of 608
Quote:
Originally Posted by poisson21 View Post

With my little understanding and poor drawing skill i'll try to "explain" how cldo_vddp work.


The curve represente your dram voltage signal, changing cldo_vddp move back and forth this signal compared to your available frequency setting.
The purpose to changing it is to make the curve crossed your setting line on the appropriate frequency setting.
Whereas the zone where there is no curve present is a memory hole .
Depending of your IMC or RAM the curve can vary in lenght or thickness.
If i understand it properly, it work like that.

Sorry for my poor english.
Quote:
Originally Posted by 1usmus View Post

All is true, only the form is more oblate, in dozens of times


Thank you both smile.gif

This makes much more sense. So that would mean the only way to difinitively tell what your ideal setting is is to have an oscilloscope tongue.gif haha otherwise trial and error... with a few 'common starting points'
Quote:
Originally Posted by 1usmus View Post

An overabundance of voltage generates digital and thermal noise, increasing the voltage can both positively and negatively affect on system. To simplify your life put vdram = vboot dram.By my observation vboot also takes part in the work of the system after training.

Сalculate СLDO_VDDP is impossible, it is always different. It is also influenced by procODT. The values that the calculator offers are values that work successfully on most systems. They are found purely in practice.

It is extremely difficult to configure the 3600. It is necessary to regulate constantly additional voltages : VPP , VDDP , PLL and VTT DDR. Increasing the voltage to SOC will not help, and in most cases worsen the situation. The controller is very sensitive to noise.

I see, so to try and get 3600 stable i'm going to need to play, and play biggrin.gif

It may not be worth my time given my system is mostly used for gaming sub 100 fps. I'm more than happy to test for the sake of knowledge though biggrin.gif
Edited by blair - 11/24/17 at 10:32am
post #360 of 608
Thread Starter 
Quote:
Originally Posted by blair View Post


Thank you both smile.gif

This makes much more sense. So that would mean the only way to difinitively tell what your ideal setting is is to have an oscilloscope tongue.gif haha otherwise trial and error... with a few 'common starting points'
I see, so to try and get 3600 stable i'm going to need to play, and play biggrin.gif

It may not be worth my time given my system is mostly used for gaming sub 100 fps. I'm more than happy to test for the sake of knowledge though biggrin.gif

The memory frequency of 3466+ is meaningless, CPU utilization and multi-core efficiency depend on the Infiniti fabrick. There comes a moment when growth stops because the core frequently reaches the limit.
At the moment the memory frequency of 3466 corresponds to the processor frequency of 4100 MHz.
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