I decided to write a small article explaining why some systems work fine at 3200+ and others do not at all
Influence of СLDO_VDDP on MEMCLK "holes"
CLDO_VDDP is a voltage regulator for the module (physical interface) of encoding and decoding of the transmitted and received data stream. The purpose of coding is to simplify the process of restoring the data stream of the receiver. It determines the signals, signal ratios and time parameters necessary for transferring control information, reading and writing data to DRAM devices. In plain language, CLDO_VDDP is the voltage that regulates the memory access at a certain frequency. "Hole" in turn - the frequency gap on which the memory controller can operate with our RAM.
Consider this simple picture:
It shows 3 identical systems (motherboard + RAM + processor). All 3 systems were overclocked and received the following results:
1) The system was perfectly dispersed to a frequency of 3333 MHz
2) The system was accelerated to 2933
3) The system did not start at all
If all systems are the same, why such results? Let's understand. The bottom line is that each memory controller (IMC) has its own technical characteristics ("voltage" and time) and at the same voltage / frequency it will behave differently, namely it will have different access to memory. Red marked our MEMCLK holes, these are the very hole-mediators through which our memory controller communicates with RAM, and if there is no hole in the frequency range chosen by us - the system does not start or start, but the memory runs with errors. At you I think there was a question as these holes to move and expand - all is very simple, voltage CLDO_VDDP allows to spend the given manipulations. The only difficulty is that these holes can not be mathematically calculated. A vivid example of CLDO_VDDP 866 which is magical for many. The hole of this voltage is in the region of 3300-3500 MHz, but again not for all systems. As shown by our internal tests, not all of it works, I repeat all the IMC are different and require a different voltage CLDO_VDDP to achieve the same frequency.
In view of the fact that the shape of the voltage CLDO_VDDP is wave, the minimum voltage change can drastically change the stability of the system. The voltage step is 1 mv. Borders from 700 to 975.
I also want to publish a list of CLDO_VDDP, which can help stabilize your memory
CLDO_VDDP list (volts) (Click to show)
In the Ryzen DRAM Calculator the recommanded CLDO_VDDP value is 425 mV no matter the type of memory you have. ALT 1 is 866 mV and ALT 2 is 945 mV. Is there an error there? You said earlier "The voltage step is 1 mv. Borders from 700 to 975." 425 mV is way lower than 700.