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[TR] Samsung teases higher-than-expected speeds from its GDDR6 RAM - Page 2

post #11 of 27
Quote:
Originally Posted by epic1337 View Post

interesting, 128bit @ 16GT/s makes for a 256GB/s bandwidth, and thats 4dies of GDDR6.
theoretically this means they can make a Polaris-tier card using only 4dies of VRAM, much more compact.


While true from a pure speccificatioin standpoint, Im not sure they would want to. Maybe for a lower end fcard, but limiting to 4 channels of vram means less channels for the render pipelines to attach to. That means a bottleneck in that area so the cards willhave a harder time even if the bandwidth is the same. Using 8 chips means you dont have to cram as many pipelines onto a single channel, and the pipelines need a whole lot of bandwidth.


Though I suppose they could do some serious tricks with L2 to mitigate the bottleneck. Im not sure thats the best solution as cache space is very expensive.
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post #12 of 27
Quote:
Originally Posted by EniGma1987 View Post

While true from a pure speccificatioin standpoint, Im not sure they would want to. Maybe for a lower end fcard, but limiting to 4 channels of vram means less channels for the render pipelines to attach to. That means a bottleneck in that area so the cards willhave a harder time even if the bandwidth is the same. Using 8 chips means you dont have to cram as many pipelines onto a single channel, and the pipelines need a whole lot of bandwidth.


Though I suppose they could do some serious tricks with L2 to mitigate the bottleneck. Im not sure thats the best solution as cache space is very expensive.

Nvidia's already cramming that much ROPs into narrower bus though.
GP104 = 64ROPs @ 256bit bus.

compared to that, AMD's is "fat".
P10 = 32ROPs @ 256bit bus.

and we all know that Nvidia's GP104 is much, much faster than AMD's P10.
edit: so how does Nvidia manage that much hardware throughput with just 256bit bus?
Edited by epic1337 - 11/10/17 at 5:33pm
post #13 of 27
Quote:
Originally Posted by epic1337 View Post

Nvidia's already cramming that much ROPs into narrower bus though.
GP104 = 64ROPs @ 256bit bus.

compared to that, AMD's is "fat".
P10 = 32ROPs @ 256bit bus.

and we all know that Nvidia's GP104 is much, much faster than AMD's P10.
edit: so how does Nvidia manage that much hardware throughput with just 256bit bus?

G104 runs at much higher clocks speed too.
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post #14 of 27
Quote:
Originally Posted by PearlJammzz View Post

HBM2 is already not a Vega exclusive technology. Nvidia uses it in its P100-series of cards. They just cost 6-10k dollars each. I also think we'll see HBM2 on some APUs soon enough. Even just 1 4GB stack would make onboard graphics amazing for what they are.

I feel HBM will always have its place. It just might not become ubiquitous as fast as some people thought it would be. Right now most of the HBM is being used by the high-end compute cards and the consumer/prosumer level cards are getting the trash chips. That'll change eventually and this new technology will evolve. There will be a tipping point but it may not be anytime soon.

They only cost $10,000 a piece because of the same logic/reasoning that a Xeon costs that much. Because Nvidia says it's worth that much, when in fact is flat out ISN'T. rolleyes.gif
     
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post #15 of 27
Quote:
Originally Posted by ZealotKi11er View Post

G104 runs at much higher clocks speed too.
exactly, GP104 runs at a much higher clock speed on top of a bigger die configuration.
despite that, both GP104 and P10 have the same 256bit bus and both are clocked at 8GT/s (256GB/s), except GTX1080 which uses GDDR5X.
post #16 of 27
Quote:
Originally Posted by SystemTech View Post

Interesting news. Whats the average speed of L1, 2 and 3 cache on CPU's these days? How big is the gap. Obviously cache still hold the latency superiority, but i think it will be interesting should the speeds get closer together.

HBM will always have its place, especially for it size and packaging.



(Not sure what's up with the L4 in this, but that was on the old motherboard back in April.)

wink.gif

I believe L1 and L2 are additive with cores, so an 8700K for instance should get about 1.3TB/s L1 and 330GB/s L2, assuming its cache structure is largely unchanged, due to the extra cores and the cache attached to them. You're looking at 1-10TB/s L1, 100-1000GB/s L2, and about 100GB/s L3, generally speaking.
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post #17 of 27
I can see Nvidia sandbagging GF Volta longer to throw GDDR6 on it instead of using HBM2. Maybe even use HBM2 on Volta Titan and GDDR6 on Ti and lower as a means to keep the Titan an ultra-halo product.
    
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post #18 of 27
Quote:
Originally Posted by PostalTwinkie View Post

I can see Nvidia sandbagging GF Volta longer to throw GDDR6 on it instead of using HBM2. Maybe even use HBM2 on Volta Titan and GDDR6 on Ti and lower as a means to keep the Titan an ultra-halo product.

16Gbps means that the next Volta lineup will all get G6. 1070 and 1060 class will probably get G5X. 1080 Ti class going from 11 to 16 is more then enough for generational jump.
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post #19 of 27
I smell GDDR6 on board Intel’s new GPU.
     
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post #20 of 27
Quote:
Originally Posted by PostalTwinkie View Post

I can see Nvidia sandbagging GF Volta longer to throw GDDR6 on it instead of using HBM2. Maybe even use HBM2 on Volta Titan and GDDR6 on Ti and lower as a means to keep the Titan an ultra-halo product.

Like 3-6 months ago hynix already said they have partner gpus coming out in the first half of 2018 with gddr6.
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