Originally Posted by FrankenPC
Please...I thought I had a weak grasp on timings. But, now I'm totally confused. Main reason? A completely different intermixing of terminology during conversations. If the terminology could be explained and nailed down, I could follow the logic much easier.
The timings as I know them(which may be wrong) are:
CL-> CAS Latency -> The time(aka # of cycles) taken between a command having been sent to the memory and when it starts to reply to the command. Which in reality is the time between the CPU requesting data from the Memory and it(data) returning to the CPU.
tRCD -> RAS to CAS delay -> The time taken between the activiation of the RAS(line) and the CAS(column), as such the data is stored in a matrix.
tRP -> RAS precharge -> the time taken between disabling access to a line of data and the start of access to a new line of data.
tRAS-> Active to precharge delay -> The time memory waits before the next access to memory can be initiated.
CMD -> Command rate -> Time between memory chip activation and the first command having been sent to memory.
Time = # of cycles
Also effective data bus speed table taken from Xbitlabs: