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Memory: Dividers, Latencies, and Bandwidth Explained - Page 6

post #51 of 57
how many bits you transfer doesn't have to deal with frequency. how many bits it transfers can rely upon a few things.
it's real speed is still 400mhz for pc6400.

EDIT: I see what your talking about. it is the actually chip speed on the chip not the memory bus speed.
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post #52 of 57
Quote:
Originally Posted by FrankenPC View Post
Please...I thought I had a weak grasp on timings. But, now I'm totally confused. Main reason? A completely different intermixing of terminology during conversations. If the terminology could be explained and nailed down, I could follow the logic much easier.
The timings as I know them(which may be wrong) are:

CL-> CAS Latency -> The time(aka # of cycles) taken between a command having been sent to the memory and when it starts to reply to the command. Which in reality is the time between the CPU requesting data from the Memory and it(data) returning to the CPU.

tRCD -> RAS to CAS delay -> The time taken between the activiation of the RAS(line) and the CAS(column), as such the data is stored in a matrix.

tRP -> RAS precharge -> the time taken between disabling access to a line of data and the start of access to a new line of data.

tRAS-> Active to precharge delay -> The time memory waits before the next access to memory can be initiated.

CMD -> Command rate -> Time between memory chip activation and the first command having been sent to memory.

Time = # of cycles


Also effective data bus speed table taken from Xbitlabs:



http://www.xbitlabs.com/articles/mem...r_2.html#sect0
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post #53 of 57
Old thread but its a good one. I was wodering if DDR2 800 have 6.4gb/s what about in dual channel. should it be double.
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post #54 of 57
I know this is old but i think this info should be added into the latency/clock cycle section as its a MUST read for everyone whos new or having trouble with ram..
Quote:
tCL:
Large influence on stability / Medium influence on bandwidth
From CAS 5 to 4 results change ~5-10mb/s. The same change will most likely be seen when going to CAS 3. This timing is widely seen as most important (Command rate disregarded).
Recommendation: 4 for normal usage, 5 when oc"ing. Tweaked: 3.


tRCD:
Medium influence on stability / Large influence on bandwidth
tRCD going from 4 to 3 gives ~15mb/s. From 5 to 4 also yields 10-15mb/s. This timing is considered second important after CAS, but actually it"s more important on 680i/DDR2.
Recommendation: 4 for oc/normal usage. 5 if you want to push mhz. Tweaked: 3


tRP:
Medium/small influence on stability / Small influence on bandwidth
Results vary close to nothing when changing from 3 to 4 to 5. Still this timing needs to finish its cycle before a new one starts, so dont set it higher than 5.
Recommendation: 4 for oc/normal usage. 5 if you want to push mhz. Tweaked: 3


tRAS:
Small influence on stability / Small influence on bandwidth
tRAS seems to act differently on integer/float results. Integer, going from 15 to 10 changes by ~5mb/s. Float doesnt change.
tRAS is an "end-timing", so dont go to high. And not lower than what tCL+tRCD equals.
Recommendation: 12 for oc/normal usage. 15 if you want to push mhz. Tweaked: 8


tRRD:
Small influence on stability / Small influence on bandwidth
tRRD of 2 didnt change the results. Nor did a tRRD of 4. This is a delay-timing so a too low value may result in recalculation.
Recommendation: Auto for oc/normal usage. 4 if you want to push mhz. Tweaked: 2


tRC:
Medium influence on stability / Large influence on bandwidth
This timing is quite surprising. Going from 30 to 21 gave ~90mb/s. From 23 to 21 gave ~15-20mb/s.
tRC is last timing before ram burst (data transfer).
Dont set too high. And tRC should be greater than tRAS + tRP or you might get corruption.
Recommendation: 21 for normal usage. 30 if you want to push mhz. Tweaked: 15


tWR:
Small influence on stability / Small influence on bandwidth
Small change from 6 to 3. Setting timing too low will cause ram to fail switching to "read mode".
Recommendation: Auto for oc/normal usage. 6 if you want to push mhz. Tweaked: 3


tWTR:
Large influence on stability / Small influence on bandwidth
From 10 to 8 didnt change results. 6 would lock up the system. This timing gives no bonus but affects stability a lot. Use with care.
Recommendation: Auto for oc/normal usage. 10 if you want to push mhz. Tweaked: 8(7)

tREF:
Small influence on stability / Small influence on bandwidth
Changing to 3,9us didnt show improvements in benchmark. It also didnt seem to affect stability. tREF was important with DDR1.
Recommendation: Auto for oc/normal usage. 7,8us if you want to push mhz. Tweaked: 3,9us


Command Rate:
Settings are 2T/1T. You probably already know a lot about this timing.
The 680i struggles running 1T above 800mhz. So do the ram - atleast 2,2v are needed. This timing gives a great boost to bandwidth, but is fairly hard to attain. I wont recommend any setting regarding this timing. You need to find what mhz you get with 1T, then find mhz with 2T, then compare benchmarks.


Post words:
The tRC and tRCD are two timings to take notice of. They yield good results compared to how they affect stability.
CAS isnt as important as in the DDR1 days. You might even say timings in generel arent as important as with DDR1.

Hope this helps everyone
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post #55 of 57
i dont get how or why you multiplied the actual memory speed by 4 after all it is a DDR2 => you should multiply it by 2 not 4
am i right?
please consider my post but dont accept it blindly after all, i am new to overclocking and i am trying to learn how this art can be mastered!

thank you,
very nice article really helped me!
post #56 of 57
The 2 in DDR2 has NOTHING to do with speed, it's just there to show that it is different to DDR.

Look at this picture again
post #57 of 57
+1 internets to you sir!
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