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AMD Phenom Die Photo - Page 5

post #41 of 52
Quote:
Originally Posted by aaronman View Post
Just got me thinking, how fast would Conroe architecture be if it was on an AMD style bus system?
You could only imagine? I would think pretty awesome but it would need HTT and complete change..

Besides all a conroe is compared to say Pent 4 is more ops / cycle. 64 bit is still emulated and lately it's been 2 C2D on one die for a C2Q.. I'm disappointed.

Still if AMD + Intel joined forces keeping the AMD bus style system with HTT 3.0 and a ton of ops / cycle at good heat rates !
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post #42 of 52
if AMD+Intel joined forces, the world would die! lol

But, meh - it'll never happen.

Computing would evolve RAPIDLY..
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post #43 of 52
I almost think technology would progress faster with competition. It's human nature to just... not work well with other people and share, so we have to beat somebody. It may as well be AMD/Intel!
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post #44 of 52
Quote:
Originally Posted by Grim View Post
Not at all.

More L3 simply means that that data, would have (had not the l3 been present) needed to come from RAM (which is further away and ALWAYS slower, OR eventually, the HDD.)

That cache being there simply means the CPU Will have access to it much quicker.

More cache is ALWAYS better
The only catch here is that more cache will mean more heat but also more importantly will mean a larger die, which will lead to higher prices since that would mean less dies per wafer and higher chance of defects per die. Plus, design of the cache will also affect it's performance. Intel uses an inclusive cache where the same data is stored on both the L1 and L2 cache. This takes up more cache but will have a much higher chance of a cache hit. AMD uses an exclusive cache where data that is bumped off L1 to L2 is erased from L1. This results in more cache for other data but will have a higher chance of a cache miss, and the chip will have to look in one and then the other cache.

Quote:
Originally Posted by aaronman View Post
Just got me thinking, how fast would Conroe architecture be if it was on an AMD style bus system?
Just wait for Nehalem in 2009 (I think). It's built up on the Core architecture with the addition of their version of Hypertransport called CSI (Common System Interface) and it also has an intregrated memory controller.

From Anandtech:

Quote:
Nehalem Micro Architecture: Intel Embraces the IMC and IGP

Surprisingly, Intel gave away quite a few details about Nehalem. Although Nehalem is still based on the 4-issue Core architecture, it takes "multithreading" to a whole new level. First of all, Nehalem can contain up to eight cores per die. Combined with 2-way Simultaneous Multi-Threading (SMT or Hyper-Threading), you'll have the ability to execute up to 16 threads on one chip!

Nehalem will also use multi-level shared cache. Pat Gelsinger indicated that only the highest level of cache would be shared, meaning that Nehalem could very well have a similar cache hierarchy to AMD's Barcelona (independent L1/L2 caches per core, but a shared L3 cache). The power of each core is "dynamically managed" which might indicate that Nehalem goes one step further than AMD's Barcelona core: it could have independent power planes.

Nehalem will no longer use a FSB but a serial point to point interconnect. Even more revolutionary is the fact that Nehalem will have an integrated memory controller (IMC) and that the number of serial interconnects is variable (Intel's version of "HyperTransport"). Another potentially groundbreaking move is that some Nehalem CPUs will have a GPU integrated (Intel's version of "Fusion"). With an integrated memory controller, new interconnect, and potentially integrated graphics, Nehalem will obviously require a new socket.

Intel would not give any more detail, but it is clear that the GPU will not be high-end (that would require too much power); more likely it will be a kind of midrange (or even low-end depending on your perspective) solution. Intel would not confirm this, but it seems pretty clear to us that Xeon DP and desktop products will probably have an IMC that supports DDR3. Xeon MPs will probably have an IMC that supports registered FB-DIMMs with DDR3. Nehalem should first be available in the second half of 2008 as Intel talked about "production ramping in 2008, with full production in 2009".
So that's basically a Core chip on AMD platform. Seems like AMD and Intel are basically producing chips that are more and more alike.....
    
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post #45 of 52
Wow that integrated memory controller is really quite revolutionary! Very nice job Intel!
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post #46 of 52
Yeah, all they need to address now is the ever present flaw in their architecture - a huge dependency on HIGH FSBs... :rollleyes:
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post #47 of 52
Why doesn't AMD put even more Cache on it like as much as C2D and they would be ahead... lol. Or not, because maybe theirs if more efficient at what theirs do, and putting more cache might hurt it?
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post #48 of 52
I really doubt it..
Its something i've wondered myself

perhaps it would have to be really highspeed cache to be significantly profitable - and that would be expensive.
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post #49 of 52
the a64 line really didn't benefit that much from higher cache, maybe it's the same here.
post #50 of 52
Quote:
Originally Posted by jonny1989 View Post
I would also whant to know how much this beast will cost.Will i have to sell my soul for this thing.I would say for the Quad core $500-$800 and for the x2 $400-$500 if not more.
Not your soul, just an arm and a leg.
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