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Intel Readies New Memory Controller for Nehalem Chips.

post #1 of 23
Thread Starter 
http://xbitlabs.com/news/cpu/display...610234912.html

Quote:
Intel Nehalem to Feature Triple-Channel Memory Controller
Intel’s code-named Nehalem processors have been discussed for nearly five years now, but Intel was tight-lipped enough in order not to disclose details of the new micro-architecture itself as well as implementation peculiarities. Nevertheless, recently Intel started to inform its partners about the future platforms, which means that at least some peculiarities of the new chips have come to light.


It is known that Nehalem as well as Westmere central processing units (CPUs) will use a new platform architecture and while the company does not directly state it, the new platform will hardly use processor system busses, but rather will feature point-to-point serial bus (which is currently referred to as Common Serial Bus or CSI) similar to Hyper-Transport or PCI Express. The new CPUs due in late 2008 will feature so-called dynamically scalable architecture, which means that Intel will be able to tailor its processor designs according to needs of various market segments.

In particular, Intel already announced that, among other things, it would be able to scale and configure caches, interconnect controllers as well as memory controllers. Already now Intel can reduce or increase cache sizes for various processors without many problems, whereas Advanced Micro Devices can enable or disable Hyper-Transport links within its processors depending on their positioning (e.g. AMD Opteron processors for multi-processor servers have three HT links, whereas Athlon 64 for 1P machines have only one HT link). But Intel wants to go even further and scale the number of memory controller channels. According to PC Watch web-site, the top Nehalem processor code-named Bloomfield with four cores will have triple-channel DDR3 memory controller, whereas slightly less advanced may have less channels.

Three memory channels supporting PC3-12800 (DDR3 1600MHz) memory would provide approximately 38.4GB/s memory bandwidth, up significantly from about 21.3GB/s memory bandwidth available today. Given that in 2009 Intel plans to release Nehalem processor with built-in graphics core, triple-channel memory controller may help to keep performance in 3D games on relatively high level.

Intel did not comment on the news-story.
Triple channel memory?!?!? Have we saturated the memory channels already??? Isn't AMD's architecture supposed to be scalable as well?
    
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post #2 of 23
Just wow... goodbye AMD..
     
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post #3 of 23
The way Intel has been pumping out chips well before planned release date I suspect we will see this in Q2/Q3 08.

Intel has yet to reach it apogee, and I think that AMD has to hit is perigee. Watch for a buyout by TI and a comeback by AMD in 2009. Until then, Intel owns the processor field.
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post #4 of 23
Before all the AMD bashing starts lets just see what AMD has to offer with K10
post #5 of 23
Quote:
Originally Posted by Bitemarks and bloodstains View Post
Before all the AMD bashing starts lets just see what AMD has to offer with K10
Didn't we already see what K10 can do? 1.6Ghz with the AMD techies sweating because they can't squeeze anything more out of it?
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post #6 of 23
Quote:
Originally Posted by pauldovi View Post
Didn't we already see what K10 can do? 1.6Ghz with the AMD techies sweating because they can't squeeze anything more out of it?
Their road maps call for up to 2.6Ghz chips. Whether or not this is the case at release time, I think it wise to reserve judgment until said time of release. Nothing is final until the chips are out the door.
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post #7 of 23
Quote:
Originally Posted by The Bartender Paradox View Post
Their road maps call for up to 2.6Ghz chips. Whether or not this is the case at release time, I think it wise to reserve judgment until said time of release. Nothing is final until the chips are out the door.
Exactly, nothing is final, including those roadmaps.

AMD hasn't demonstrated anything higher than 1.6Ghz. We are just weeks away from the launch. If AMD is only running 1.6Ghz (and trust me, that is all they are getting out of this), what do you think they will be able to get in a few weeks? No more than 2.0Ghz. And how do you suspect that this will overclock if AMD is getting 1Ghz less than what their roadmap shows weeks out of a launch?

Intel demoed a Penyryn @ 3.33Ghz in April 07 even those it isn't launching until Q1 08! That is some 36 weeks away from its launch. We are just 6-8 weeks away from the "launch" of Barcelona and we aren't even getting anywhere near their roadmap.
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post #8 of 23
Lol

AMD is in trouble...

And triple channel memory... 4 cores... hawt

But they had me at CSI: Crime Scene Investigation
post #9 of 23
Well, one thing here fellas, the Bully allways flexes....

And the nerd trains and trains until he is uber and whoops the bully...

we will see...
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post #10 of 23
Thread Starter 
Technically speaking, I don't see Intel having triple channel memory as any kind of threat to AMD, since each individual core in the K8/K10 architecture does have its own memory controller so AMD can potentially unleash more than one controller, but the more important question here is, do we really need it? I think AMD's plan to run the memory controller faster than the core clock is more beneficial than Intel's plan to run another memory channel.
    
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