post #21 of 21
Quote:
Originally Posted by Licht View Post
Yes but this happens less overall in AMD CPU.
No, it happens more often in a K8 based CPU compared to a Core 2.

When it comes to developing a processor architecture designers need to look at the way that various algorithms, such as a branch prediction, should be approached. If an architecture is able to implement a branch prediction correctly then the processor won't have to flush the pipeline and reload the data before continueing with the instruction stream. This is all down to improvements made in the overall instructions per clock. Now seeing as it is well known that Core 2's perform more instructions per clock, when compared to current Athlon 64's and X2's, your argument seems somewhat shallow. Unless you were comparing a K8 to a Netburst of course.