Originally Posted by Shadowrunner340
leave it to open source to criticize something you have to pay for. of course, i haven't checked, but i've never heard anyone complain about C2D processsors. i've had mine for a few months, and never once had a problem. on the other side of the coin, i've never heard anyone complain about AMD either (fanboyism aside, of course)
lol, they are pointing out what the hell is wrong since the people who you paid so much to don't want to tell you the specifics of it so you keep on buying their stuff
Originally Posted by ClaytonCallihan
Man, all those bugs and those cpu's still rape everything. Imagine if it was all fixed...
Then you would have a same speed CPU with no security loop holes
Originally Posted by bdattilo
Hmmm.....interesting. I wonder how Intel will respond? If this is true, they might have to do a recall, but I can't see Intel recalling all C2D's.
They did respond, they released a patch to fix a few errors.
Originally Posted by nuclearjock
Looks ok for graphics
Let's see, todays score:
Intel = 30
AMD = 0
Maybe you should read what the non-fixable bug's really are and how they affect your CPU
When the temperature reaches an invalid temperature the CPU does not generate a Thermal interrupt even if a programmed threshold is crossed.
I donâ€™t see how this is a security concern; maybe he meant AI56, which gives unpredictable behavior if you change the attributes of a PTE without fixing up the TLB; AI64 involves system management mode and AI67 involves VTX.
During a series of REP (repeat) store instructions a store may try to dispatch to memory prior to the actual completion of the instruction. This behavior depends on the execution order of the instructions, the timing of a speculative jump and the timing of an uncacheable memory store. [â€¦] When this erratum occurs, the processor may live lock and/or result in a system hang.
Unless the behavior depends on system memory inaccessible to userland, this could imply userland crasher exploit.
When a logical processor writes to a non-dirty page, and another logical- processor either writes to the same non-dirty page or explicitly sets the dirty bit in the corresponding page table entry, complex interaction with internal processor activity may cause unpredictable system behavior [â€¦] and hang.
Two userland processes on two different cores can race each other and hang the system?
When request for data from Core 1 results in a L1 cache miss, the request is sent to the L2 cache. If this request hits a modified line in the L1 data cache of Core 2, certain internal conditions may cause incorrect data to be returned to the Core 1.
Where the word â€œincorrect dataâ€ is errata code for â€œZuulâ€™s return as the Sta-Puft Marshmellow Manâ€ â€”- two cores race each other, and a process gets the wrong cache line.
If code segment limit is set close to the end of a code page, then due to this erratum the memory page Access bit (A bit) may be set for the subsequent page prior to general protection fault on code segment limit. [â€¦] a non-accessed page which is present in memory and follows a page that contains the code segment limit may be tagged as accessed.
Theo says this is exploitable on operating systems other than OBSD; the A bit signals the VM system that a page has been accessed by the hardware.
Code #PF (Page Fault exception) is normally handled in lower priority order relative to both code #DB (Debug Exception) and code Segment Limit Violation #GP (General Protection Fault). Due to this erratum, code #PF may be handled incorrectly, if all of the following conditions are met:
A PDE (Page Directory Entry) is modified without invalidating the corresponding TLB (Translation Look-aside Buffer) entry
Code execution transitions to a different code page such that both:
The target linear address corresponds to the modified PDE
The PTE (Page Table Entry) for the target linear address has an A (Accessed) bit that is clear
One of the following simultaneous exception conditions is present following the code transition:
Code #DB and code #PF
Code Segment Limit Violation #GP and code #PF
Software may observe either incorrect processing of code #PF before code Segment Limit Violation #GP or processing of code #PF in lieu of code #DB.
People are going to be all over these bug's like virus's and windows.
If I had a C2D I would try to get my money back and when the next line of fixed CPU's come out get one of them.