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Intel preps 'Tigerton' Xeons for September

post #1 of 12
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Quote:
If Barcelona indeed comes in September as we've heard, it may arrive just in time to face renewed competition from Intel. According to DigiTimes, Intel plans to introduce a set of "Tigerton" processors intended for four-way servers some time at the start of September.

Tigerton CPUs will essentially be spinoffs of Intel's Core-based Xeons tweaked for operation in 4P systems. DigiTimes says the Tigerton lineup will include quad-core models clocked between 1.86GHz and 2.93GHz with either 4MB or 8MB of cache as well as dual-core models running at 2.4GHz and 2.93GHz with 8MB of cache. Prices will range from $856 for the cheapest dual-core model to a whopping $2,301 for the 2.93GHz quad-core part. Today, Intel's only 4P-capable parts are still based on the old Netburst architecture.
[Source: The Tech Report]
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post #2 of 12
Sweet I about got a boner and died when i heard they make 3.4ghz netburst server chips! with 16meg L2 thats like dying and going to heaven, I want one so damn bad, no fair.
    
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post #3 of 12
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Originally Posted by Devon View Post
Sweet I about got a boner and died when i heard they make 3.4ghz netburst server chips! with 16meg L2 thats like dying and going to heaven, I want one so damn bad, no fair.
Still, The L2 cache is shared between the two cores on the same die, but not shared across dies. & that too bad.
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post #4 of 12
aww thats fine i only want super fast netburst performance and high power comsumption, i also want to play half life 2
    
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post #5 of 12
Geeze, 2300 dollars. Wouldnt this be the god of all processors? How long before you can pop one into your desktop for a reasonable price?
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post #6 of 12
So this means you can now have 16 cores and 32MB L2 for just an arm and a leg and an eye?
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post #7 of 12
Quote:
Originally Posted by Fishie36 View Post
So this means you can now have 16 cores and 32MB L2 for just an arm and a leg and an eye?
I'm thinking both eyes lol
    
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post #8 of 12
I hope they add more than 1 memory bus...16 cores fighting over 1 memory bus could get ugly.
Very nice!
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Very nice!
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post #9 of 12
Quote:
Originally Posted by J3r3my View Post
I hope they add more than 1 memory bus...16 cores fighting over 1 memory bus could get ugly.

Cat fight.
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post #10 of 12
It will probably have quad independent FSBs to handle all of that traffic. That's going to be a crapload of bandwidth to feed all of those cores. Can't wait to see how the MCM scales, depending on how Intel chooses to design the FSB structure.
    
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