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Cache and memory in the many-core era

post #1 of 21
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Quote:
Introduction

One of the greatest challenges facing the designers of many-core processors is resource contention. The chart below visually lays out the problem of resource contention, but for most of us the idea is intuitively easy to grasp: more cores and more simultaneous threads means more contention for shared resources, specifically cache space and memory bandwidth...
Quote:
As Moore's Law increases, the amount of parallel hardware and the number of threads that can access a single, shared resource, this problem will continue to grow. Indeed, resource contention challenges have the potential to scale fairly well with increases in core and thread counts, so chip multiprocessor (CMP) designers have been working on ways to address this issue since the very start of the dual-core era...
http://arstechnica.com/articles/paed...-many-core.ars
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post #2 of 21
i'll bet the only word coming out of Intel's and Amd's mouth is "woops?"
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post #3 of 21
Quote:
Originally Posted by johonm333 View Post
i'll bet the only word coming out of Intel's and Amd's mouth is "woops?"
Intel has 16mb
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post #4 of 21
Quote:
Originally Posted by johonm333 View Post
i'll bet the only word coming out of Intel's and Amd's mouth is "woops?"
Yea, good read.
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post #5 of 21
I wanna say something about HT, it is on the tip of my tongue...
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post #6 of 21
Quote:
Originally Posted by johonm333 View Post
i'll bet the only word coming out of Intel's and Amd's mouth is "woops?"
AMD isn't mentioned?
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post #7 of 21
Quote:
Originally Posted by MGX1016 View Post
AMD isn't mentioned?
Neither was Intel.

"chip multiprocessor (CMP) designers"

Anyone who makes multiprocessor chips. That's AMD also.
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post #8 of 21
Sounds like they are poking fun at AMD's. correct me if I am wrong, but all of the AMD chips use separate caches for each core. Intel chips use shared cache, allowing the two cores to talk to each other.
    
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post #9 of 21
Quote:
Originally Posted by Modki View Post
Neither was Intel.

"chip multiprocessor (CMP) designers"

Anyone who makes multiprocessor chips. That's AMD also.
They do Specifically mention Intel, look at the last page, in the concluding paragraph.
    
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post #10 of 21
Quote:
Originally Posted by trueg50 View Post
Sounds like they are poking fun at AMD's. correct me if I am wrong, but all of the AMD chips use separate caches for each core. Intel chips use shared cache, allowing the two cores to talk to each other.
Nope... For current quad-core, more like the other way around. Intel current implementation is two dual cores next to each other. Each core has a dedicated L1 cache and a shared L2... then it uses the FSB so the two sets of cores can communicate. AMD's implementation will give each core a L1 and L2 cache. There is a L3 cache that will be shared between all four cores. AMD's current design is better at scaling. Intel of course will have a new architecture next year though.
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