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6 GHz SRAM Memory Introduced By IBM - Page 2

post #11 of 26
Quote:
Originally Posted by DuckieHo View Post
No.... cache speed and FSB have nothing to do with each other. Main memory RAM and FSB are related.

L1 is super fast/expensive memory. L2 is very fast memory. Both are intergrated into the CPU. Then there is main memory or "RAM".
Are you positive? I could have sworn I read somewhere on here that L1 speed=CPU speed, and FSB speed=L2 speed. *goes a searching*
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post #12 of 26
L1 is godly fast. Thats all i know. Thats why you can't get more than 100Kb of it.
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post #13 of 26
I dont think any of you know mybe i should research this a bit and report back lol.
post #14 of 26
Quote:
Originally Posted by pauldovi View Post
[B](Version 1.10)


The FSB is the speed of the L2 (level 2) cache. L2 Cache is largest chunk (desktop CPUs only) of memory on the CPU. This is what directly communicates with your system memory. From the L2 cache the data is moved to the much smaller, but also much faster L1 (level 1) cache. CPU speed is normally referred to as the speed of the L1 cache.

In order to determine your CPU speed, you multiply the FSB by its multiplier.

For example:

266.66Mhz FSB x 9 = 2.40Ghz

The 2.40Ghz is the speed of the L1 cache.
From pauldovi's overclocking post.
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post #15 of 26
I think they still seem to think Mhz is everything. Take a 2.0 Ghz core2 and compare it to a P4 EE at 3.6( or did they run at 3.4?) You can still say the same thing about memory, I know it is new and all but in most cases ddr3 is slower than ddr2, which is why they're making them so fast with better production, but not better design?? Hell by the time it matters though we probably will have moved onto some new wave of the future technology for RAM.
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post #16 of 26
Quote:
Originally Posted by bl!nk View Post
From pauldovi's overclocking post.
Hmmm... does this apply to K8 architecture since they don't use a FSB?
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post #17 of 26
I think what pauldovi was trying to say is the L2 access time is dependant on your FSB.

In other words, the higher the FSB, the faster data arrives and can be processed through the L2.

L2 memory itself I doubt is classified in mhz terms, it would seem more logical for it to be classified in nano second access times.
    
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post #18 of 26
Quote:
Originally Posted by Whodie View Post
I think what pauldovi was trying to say is the L2 access time is dependant on your FSB.

In other words, the higher the FSB, the faster data arrives and can be processed through the L2.

L2 memory itself I doubt is classified in mhz terms, it would seem more logical for it to be classified in nano second access times.

Hmm, makes sense.
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post #19 of 26
Quote:
Originally Posted by Whodie View Post
I think what pauldovi was trying to say is the L2 access time is dependant on your FSB.

In other words, the higher the FSB, the faster data arrives and can be processed through the L2.

L2 memory itself I doubt is classified in mhz terms, it would seem more logical for it to be classified in nano second access times.
Well.... nanosecound access time = 1/MHz
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post #20 of 26
L1 is the closest cache to the core. L2 is second closest and largest on current chips. L3 is AMD quad core only (i think maybe some xeons or C2Q but im not sure) and is used for all chips, it is the largest on the die and furthest from the core(s.) L1 is fastest since it is all about latency and the cache controller has less to control. L2 is second and L3 third int he same manners.

The above was for those asking questions about L caches.
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