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6 GHz SRAM Memory Introduced By IBM - Page 3

post #21 of 26
Quote:
Originally Posted by Licht View Post
L1 is the closest cache to the core. L2 is second closest and largest on current chips. L3 is AMD quad core only (i think maybe some xeons or C2Q but im not sure) and is used for all chips, it is the largest on the die and furthest from the core(s.) L1 is fastest since it is all about latency and the cache controller has less to control. L2 is second and L3 third int he same manners.

The above was for those asking questions about L caches.
An old Intel chip had L3 as well.
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post #22 of 26
Building on what Licht said - L1 and L2 cache run at core speed. The difference being that L1 is very close to the core and L2 is farther away from the core so L2 will have a higher latency. L3 cache resides even farther away than L2 and so will have even higher latencies than L2. L3 cache has been used before in previous P4 Extreme chips and are used in Itanium chips. AMD is also using L3 in their quad-core chip but since that has yet to be released, we won't know how their L3 performs.

The FSB is the bus that the chip uses to communicate with the Northbridge and runs much much slower than the core speed, which is why the cache is there in the first place to reduce the bottleneck of the slow data transfer.

The potential problem with this stuff is that it has a higher transistor count per SRAM cell than the normal SRAM cells. The SRAM cells are 6T SRAM arrays so that each SRAM cell uses 6 transistors whereas these are 8 transistors per cell, representing a third more resources. Thus, 6MBs of this stuff will use the same number of transistors as 8MBs of the regular transistors. So if this is carried over to CPU use, we'll either see much smaller amounts of this stuff or the chips will be a LOT more expensive since the die size will be much bigger.

To give you a rough idea of latencies:

Register's = ~0.5-2.0ns
Level 1 Cache = ~1.0-4.0ns
Level 2 Cache = ~5.0-20.0ns
Level 3 Cache = ~20.0-30.0ns
Main Memory = 35.0-50.0ns
Hard Drive = 5.0-10.0ms

Taken from a post by The_Manual
    
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post #23 of 26
Quote:
Originally Posted by Whodie View Post
I think what pauldovi was trying to say is the L2 access time is dependant on your FSB.
Technically pauldovi is wrong. L1 runs at 1:1 with your CPU speed in modern CPUs, but it didn't always.

Grabbing numbers from the air, I seem to recall 1:1 and 1:40. 1:1 is L1, 1:40 is L3(snagged that from an article about why a specific server board sucked; it had on-motherboard L3 that was slower than PC1600 memory). AMD's Quad-core L3 is much much faster, since it's still located on the die.

Sometime around when P3's were out, Intel made a CPU that ran the L1 at a ratio, in an attempt to let the rest of the CPU reach a much higher speed.
     
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post #24 of 26
Quote:
Sometime around when P3's were out, Intel made a CPU that ran the L1 at a ratio, in an attempt to let the rest of the CPU reach a much higher speed.
How effective was it?
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post #25 of 26
Quote:
Originally Posted by Licht View Post
How effective was it?
It had horrible performance per ghz, sometimes falling behind the ~450mhz P3's. Can't quite recall which, but the ratio was either 1:2 or 1:2.5

I think it might've been 1:2.5, which means often it skipped even more clocks.

But that was the beginning of the 'More clockspeed!' era, so for marketing at the time, it made sense.
     
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post #26 of 26
Quote:
Originally Posted by Cheetos316 View Post
Building on what Licht said - L1 and L2 cache run at core speed. The difference being that L1 is very close to the core and L2 is farther away from the core so L2 will have a higher latency. L3 cache resides even farther away than L2 and so will have even higher latencies than L2. L3 cache has been used before in previous P4 Extreme chips and are used in Itanium chips. AMD is also using L3 in their quad-core chip but since that has yet to be released, we won't know how their L3 performs.

The FSB is the bus that the chip uses to communicate with the Northbridge and runs much much slower than the core speed, which is why the cache is there in the first place to reduce the bottleneck of the slow data transfer.

The potential problem with this stuff is that it has a higher transistor count per SRAM cell than the normal SRAM cells. The SRAM cells are 6T SRAM arrays so that each SRAM cell uses 6 transistors whereas these are 8 transistors per cell, representing a third more resources. Thus, 6MBs of this stuff will use the same number of transistors as 8MBs of the regular transistors. So if this is carried over to CPU use, we'll either see much smaller amounts of this stuff or the chips will be a LOT more expensive since the die size will be much bigger.

To give you a rough idea of latencies:

Register's = ~0.5-2.0ns
Level 1 Cache = ~1.0-4.0ns
Level 2 Cache = ~5.0-20.0ns
Level 3 Cache = ~20.0-30.0ns
Main Memory = 35.0-50.0ns
Hard Drive = 5.0-10.0ms

Taken from a post by The_Manual
actually if i recall. the latencies have nothing to do with the distance from the core (almost) but the fact that.

the cpu core looks first at l1 for data
then l2
then l3 (if it exists)
then ram.

but if the data is found in l1 it doesnt have to go clear threw l2-ram to find it. causing it to be able to process it faster!

im sure other factors apply i.e. the speed of that cache/etc
    
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