Originally Posted by trueg50
so are those "simulated speeds" or actual?
Those are actual speeds. Intel actually demonstrated these chips back in April...
Originally Posted by ryboto
how different? I thought they were just adding SSE4 to Core 2 arch...
edit: and a die shrink..
Penryn is more than just a die shrink. Penryn introduces the worlds first 45nm Hi-k and metal gate process technology.
Compared to today's 65nm technology, Intel's 45nm technology will provide the following product benefits:
- Approximately twice the transistor density (great for smaller chip sizes or increased transistor counts)
- Approximately 30 percent reduction in transistor-switching power
- Greater than 20 percent improvement in transistor-switching speed or a greater than 5 times reduction in source-drain leakage power
- Greater than 10 times reduction in transistor gate oxide leakage for lower power requirements and increased battery life
The industry has been using silicon dioxide (SiO2) to build transistor gate dielectrics. Intel's SiO2 gate dielectrics, which have been the thinnest in the industry for the past 14 years, are now only 1.2nm thick (equal to 5 atomic layers) in our 65nm process. However, as the gate dielectric gets thinner, leakage increases. Transistor gate leakage associated with the ever-thinning gate dielectric made of SiO2 has been recognized by the industry as one of the most formidable technical challenges facing Moore's Law in this decade. Intel's solution is to move to alternate materials that are thicker to address leakage, yet at the same time preserve the high capacitance that is desirable for good transistor performance. This class of materials have a property known by the moniker "high-k." High-k, though, is not to be confused with low-k, which is being used to insulate on-chip interconnects. In transistor gate dielectrics, high-k is desirable as it gives high performance with low leakage; in interconnects, low-k is desirable as it leads to faster signal transmission times.
For its 45nm technology, Intel is using a hafnium-based high-k material in the gate dielectric. The high-k dielectric is created using atomic layer deposition (ALD) whereby a single layer of the high-k material molecule is deposited at a time. Because the high-k gate dielectric isn't compatible with today's silicon gate electrode, Intel had to develop the new metal gate materials to solve two fundamental problems that arise when the two are combined. One is known as "threshold voltage pinning" (also called "Fermi level pinning") and the other is "phonon scattering." Neither of these effects is desirable and both cause lower transistor performance. These effects arise when a high-k dielectric is used with a polysilicon gate electrode, but are significantly improved when polysilicon is replaced by specific metals (different ones for NMOS and PMOS transistors), and all are integrated with the right process recipe. (The specific metals are a trade secret.)
The combination of the metal gates and the high-k gate dielectric leads to transistors with very low current leakage and high performance.
Intel will use copper wires with a low-k dielectric for its 45nm interconnects for increased performance and lower power consumption. We will also use innovative design rules and advanced mask techniques to extend the use of 193nm dry lithography because of its cost advantages and high-volume manufacturing capabilities.
The Hi-K technology is quite revolutionary. It will allow for significantly more efficient CPUs out of the Core 2 and Core 3 architecture. Facts about 45nm Hi-k
However, Intel also introduces full SSE4 multimedia instructions, several new power saving features, and the ability to clock each individual core.
Penyrn will be quite the chip before Nehlam.